mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-18 16:08:53 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
529 lines
15 KiB
C
529 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <asm/arch/clock_manager.h>
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#include <wait_bit.h>
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static const struct socfpga_clock_manager *clock_manager_base =
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(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
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/*
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* function to write the bypass register which requires a poll of the
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* busy bit
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*/
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static void cm_write_bypass(u32 val)
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{
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writel(val, &clock_manager_base->bypass);
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cm_wait_for_fsm();
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}
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/* function to write the ctrl register which requires a poll of the busy bit */
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static void cm_write_ctrl(u32 val)
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{
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writel(val, &clock_manager_base->ctrl);
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cm_wait_for_fsm();
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}
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/* function to write a clock register that has phase information */
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static int cm_write_with_phase(u32 value, const void *reg_address, u32 mask)
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{
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int ret;
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/* poll until phase is zero */
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ret = wait_for_bit_le32(reg_address, mask, false, 20000, false);
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if (ret)
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return ret;
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writel(value, reg_address);
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return wait_for_bit_le32(reg_address, mask, false, 20000, false);
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}
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/*
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* Setup clocks while making no assumptions about previous state of the clocks.
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*
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* Start by being paranoid and gate all sw managed clocks
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* Put all plls in bypass
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* Put all plls VCO registers back to reset value (bandgap power down).
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* Put peripheral and main pll src to reset value to avoid glitch.
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* Delay 5 us.
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* Deassert bandgap power down and set numerator and denominator
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* Start 7 us timer.
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* set internal dividers
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* Wait for 7 us timer.
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* Enable plls
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* Set external dividers while plls are locking
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* Wait for pll lock
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* Assert/deassert outreset all.
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* Take all pll's out of bypass
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* Clear safe mode
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* set source main and peripheral clocks
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* Ungate clocks
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*/
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int cm_basic_init(const struct cm_config * const cfg)
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{
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unsigned long end;
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int ret;
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/* Start by being paranoid and gate all sw managed clocks */
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/*
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* We need to disable nandclk
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* and then do another apb access before disabling
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* gatting off the rest of the periperal clocks.
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*/
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writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
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readl(&clock_manager_base->per_pll.en),
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&clock_manager_base->per_pll.en);
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/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
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writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
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CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
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CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
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CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
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CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
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CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
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&clock_manager_base->main_pll.en);
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writel(0, &clock_manager_base->sdr_pll.en);
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/* now we can gate off the rest of the peripheral clocks */
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writel(0, &clock_manager_base->per_pll.en);
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/* Put all plls in bypass */
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cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
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CLKMGR_BYPASS_MAINPLL);
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/* Put all plls VCO registers back to reset value. */
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writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
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~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
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&clock_manager_base->main_pll.vco);
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writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
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~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
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&clock_manager_base->per_pll.vco);
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writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
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~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
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&clock_manager_base->sdr_pll.vco);
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/*
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* The clocks to the flash devices and the L4_MAIN clocks can
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* glitch when coming out of safe mode if their source values
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* are different from their reset value. So the trick it to
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* put them back to their reset state, and change input
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* after exiting safe mode but before ungating the clocks.
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*/
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writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
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&clock_manager_base->per_pll.src);
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writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
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&clock_manager_base->main_pll.l4src);
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/* read back for the required 5 us delay. */
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readl(&clock_manager_base->main_pll.vco);
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readl(&clock_manager_base->per_pll.vco);
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readl(&clock_manager_base->sdr_pll.vco);
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/*
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* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
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* with numerator and denominator.
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*/
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writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
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writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
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writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
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/*
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* Time starts here. Must wait 7 us from
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* BGPWRDN_SET(0) to VCO_ENABLE_SET(1).
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*/
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end = timer_get_us() + 7;
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/* main mpu */
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writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
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/* altera group mpuclk */
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writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
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/* main main clock */
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writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
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/* main for dbg */
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writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
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/* main for cfgs2fuser0clk */
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writel(cfg->cfg2fuser0clk,
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&clock_manager_base->main_pll.cfgs2fuser0clk);
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/* Peri emac0 50 MHz default to RMII */
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writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
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/* Peri emac1 50 MHz default to RMII */
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writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
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/* Peri QSPI */
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writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
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writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
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/* Peri pernandsdmmcclk */
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writel(cfg->mainnandsdmmcclk,
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&clock_manager_base->main_pll.mainnandsdmmcclk);
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writel(cfg->pernandsdmmcclk,
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&clock_manager_base->per_pll.pernandsdmmcclk);
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/* Peri perbaseclk */
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writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
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/* Peri s2fuser1clk */
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writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
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/* 7 us must have elapsed before we can enable the VCO */
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while (timer_get_us() < end)
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;
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/* Enable vco */
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/* main pll vco */
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writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
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&clock_manager_base->main_pll.vco);
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/* periferal pll */
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writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
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&clock_manager_base->per_pll.vco);
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/* sdram pll vco */
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writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
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&clock_manager_base->sdr_pll.vco);
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/* L3 MP and L3 SP */
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writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
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writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
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writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
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/* L4 MP, L4 SP, can0, and can1 */
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writel(cfg->perdiv, &clock_manager_base->per_pll.div);
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writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
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cm_wait_for_lock(LOCKED_MASK);
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/* write the sdram clock counters before toggling outreset all */
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writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
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&clock_manager_base->sdr_pll.ddrdqsclk);
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writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
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&clock_manager_base->sdr_pll.ddr2xdqsclk);
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writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
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&clock_manager_base->sdr_pll.ddrdqclk);
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writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
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&clock_manager_base->sdr_pll.s2fuser2clk);
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/*
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* after locking, but before taking out of bypass
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* assert/deassert outresetall
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*/
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u32 mainvco = readl(&clock_manager_base->main_pll.vco);
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/* assert main outresetall */
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writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
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&clock_manager_base->main_pll.vco);
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u32 periphvco = readl(&clock_manager_base->per_pll.vco);
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/* assert pheriph outresetall */
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writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
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&clock_manager_base->per_pll.vco);
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/* assert sdram outresetall */
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writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
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CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
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&clock_manager_base->sdr_pll.vco);
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/* deassert main outresetall */
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writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
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&clock_manager_base->main_pll.vco);
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/* deassert pheriph outresetall */
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writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
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&clock_manager_base->per_pll.vco);
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/* deassert sdram outresetall */
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writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
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&clock_manager_base->sdr_pll.vco);
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/*
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* now that we've toggled outreset all, all the clocks
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* are aligned nicely; so we can change any phase.
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*/
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ret = cm_write_with_phase(cfg->ddrdqsclk,
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&clock_manager_base->sdr_pll.ddrdqsclk,
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CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
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if (ret)
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return ret;
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/* SDRAM DDR2XDQSCLK */
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ret = cm_write_with_phase(cfg->ddr2xdqsclk,
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&clock_manager_base->sdr_pll.ddr2xdqsclk,
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CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
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if (ret)
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return ret;
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ret = cm_write_with_phase(cfg->ddrdqclk,
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&clock_manager_base->sdr_pll.ddrdqclk,
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CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
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if (ret)
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return ret;
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ret = cm_write_with_phase(cfg->s2fuser2clk,
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&clock_manager_base->sdr_pll.s2fuser2clk,
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CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
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if (ret)
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return ret;
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/* Take all three PLLs out of bypass when safe mode is cleared. */
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cm_write_bypass(0);
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/* clear safe mode */
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cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
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/*
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* now that safe mode is clear with clocks gated
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* it safe to change the source mux for the flashes the the L4_MAIN
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*/
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writel(cfg->persrc, &clock_manager_base->per_pll.src);
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writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
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/* Now ungate non-hw-managed clocks */
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writel(~0, &clock_manager_base->main_pll.en);
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writel(~0, &clock_manager_base->per_pll.en);
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writel(~0, &clock_manager_base->sdr_pll.en);
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/* Clear the loss of lock bits (write 1 to clear) */
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writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
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CLKMGR_INTER_MAINPLLLOST_MASK,
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&clock_manager_base->inter);
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return 0;
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}
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static unsigned int cm_get_main_vco_clk_hz(void)
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{
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u32 reg, clock;
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/* get the main VCO clock */
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reg = readl(&clock_manager_base->main_pll.vco);
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clock = cm_get_osc_clk_hz(1);
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clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
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CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
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clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
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CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
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return clock;
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}
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static unsigned int cm_get_per_vco_clk_hz(void)
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{
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u32 reg, clock = 0;
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/* identify PER PLL clock source */
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reg = readl(&clock_manager_base->per_pll.vco);
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reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
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CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
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if (reg == CLKMGR_VCO_SSRC_EOSC1)
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clock = cm_get_osc_clk_hz(1);
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else if (reg == CLKMGR_VCO_SSRC_EOSC2)
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clock = cm_get_osc_clk_hz(2);
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else if (reg == CLKMGR_VCO_SSRC_F2S)
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clock = cm_get_f2s_per_ref_clk_hz();
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/* get the PER VCO clock */
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reg = readl(&clock_manager_base->per_pll.vco);
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clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
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CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
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clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
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CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
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return clock;
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}
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unsigned long cm_get_mpu_clk_hz(void)
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{
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u32 reg, clock;
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clock = cm_get_main_vco_clk_hz();
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/* get the MPU clock */
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reg = readl(&clock_manager_base->altera.mpuclk);
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clock /= (reg + 1);
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reg = readl(&clock_manager_base->main_pll.mpuclk);
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clock /= (reg + 1);
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return clock;
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}
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unsigned long cm_get_sdram_clk_hz(void)
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{
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u32 reg, clock = 0;
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/* identify SDRAM PLL clock source */
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reg = readl(&clock_manager_base->sdr_pll.vco);
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reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
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CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
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if (reg == CLKMGR_VCO_SSRC_EOSC1)
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clock = cm_get_osc_clk_hz(1);
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else if (reg == CLKMGR_VCO_SSRC_EOSC2)
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clock = cm_get_osc_clk_hz(2);
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else if (reg == CLKMGR_VCO_SSRC_F2S)
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clock = cm_get_f2s_sdr_ref_clk_hz();
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/* get the SDRAM VCO clock */
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reg = readl(&clock_manager_base->sdr_pll.vco);
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clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
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CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
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clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
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CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
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/* get the SDRAM (DDR_DQS) clock */
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reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
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reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
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CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
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clock /= (reg + 1);
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return clock;
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}
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unsigned int cm_get_l4_sp_clk_hz(void)
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{
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u32 reg, clock = 0;
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/* identify the source of L4 SP clock */
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reg = readl(&clock_manager_base->main_pll.l4src);
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reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
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CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
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if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
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clock = cm_get_main_vco_clk_hz();
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/* get the clock prior L4 SP divider (main clk) */
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reg = readl(&clock_manager_base->altera.mainclk);
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clock /= (reg + 1);
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reg = readl(&clock_manager_base->main_pll.mainclk);
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clock /= (reg + 1);
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} else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
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clock = cm_get_per_vco_clk_hz();
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/* get the clock prior L4 SP divider (periph_base_clk) */
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reg = readl(&clock_manager_base->per_pll.perbaseclk);
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clock /= (reg + 1);
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}
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/* get the L4 SP clock which supplied to UART */
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reg = readl(&clock_manager_base->main_pll.maindiv);
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reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
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CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
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clock = clock / (1 << reg);
|
|
|
|
return clock;
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|
}
|
|
|
|
unsigned int cm_get_mmc_controller_clk_hz(void)
|
|
{
|
|
u32 reg, clock = 0;
|
|
|
|
/* identify the source of MMC clock */
|
|
reg = readl(&clock_manager_base->per_pll.src);
|
|
reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
|
|
CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
|
|
|
|
if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
|
|
clock = cm_get_f2s_per_ref_clk_hz();
|
|
} else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
|
|
clock = cm_get_main_vco_clk_hz();
|
|
|
|
/* get the SDMMC clock */
|
|
reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
|
|
clock /= (reg + 1);
|
|
} else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
|
|
clock = cm_get_per_vco_clk_hz();
|
|
|
|
/* get the SDMMC clock */
|
|
reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
|
|
clock /= (reg + 1);
|
|
}
|
|
|
|
/* further divide by 4 as we have fixed divider at wrapper */
|
|
clock /= 4;
|
|
return clock;
|
|
}
|
|
|
|
unsigned int cm_get_qspi_controller_clk_hz(void)
|
|
{
|
|
u32 reg, clock = 0;
|
|
|
|
/* identify the source of QSPI clock */
|
|
reg = readl(&clock_manager_base->per_pll.src);
|
|
reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
|
|
CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
|
|
|
|
if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
|
|
clock = cm_get_f2s_per_ref_clk_hz();
|
|
} else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
|
|
clock = cm_get_main_vco_clk_hz();
|
|
|
|
/* get the qspi clock */
|
|
reg = readl(&clock_manager_base->main_pll.mainqspiclk);
|
|
clock /= (reg + 1);
|
|
} else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
|
|
clock = cm_get_per_vco_clk_hz();
|
|
|
|
/* get the qspi clock */
|
|
reg = readl(&clock_manager_base->per_pll.perqspiclk);
|
|
clock /= (reg + 1);
|
|
}
|
|
|
|
return clock;
|
|
}
|
|
|
|
unsigned int cm_get_spi_controller_clk_hz(void)
|
|
{
|
|
u32 reg, clock = 0;
|
|
|
|
clock = cm_get_per_vco_clk_hz();
|
|
|
|
/* get the clock prior L4 SP divider (periph_base_clk) */
|
|
reg = readl(&clock_manager_base->per_pll.perbaseclk);
|
|
clock /= (reg + 1);
|
|
|
|
return clock;
|
|
}
|
|
|
|
/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
|
|
int dw_spi_get_clk(struct udevice *bus, ulong *rate)
|
|
{
|
|
*rate = cm_get_spi_controller_clk_hz();
|
|
|
|
return 0;
|
|
}
|
|
|
|
void cm_print_clock_quick_summary(void)
|
|
{
|
|
printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
|
|
printf("DDR %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
|
|
printf("EOSC1 %8d kHz\n", cm_get_osc_clk_hz(1) / 1000);
|
|
printf("EOSC2 %8d kHz\n", cm_get_osc_clk_hz(2) / 1000);
|
|
printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000);
|
|
printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000);
|
|
printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
|
|
printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
|
|
printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
|
|
printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
|
|
}
|