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![Rostislav Lisovy](/assets/img/avatar_default.png)
OMAP GPMC driver used with some NAND Flash devices (e.g. Spansion S34ML08G1) causes that U-boot shows hundreds of 'nand: bit-flip corrected' error messages. Possible cause was discussed in the mailinglist thread: http://lists.denx.de/pipermail/u-boot/2014-April/177508.html The issue was partially fixed with the cc81a5291910d7a.git however this has to be done to fix the SPL. The original author of the code is Belisko Marek <marek.belisko@gmail.com> Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
231 lines
5.7 KiB
C
231 lines
5.7 KiB
C
/*
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* (C) Copyright 2012
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* Konstantin Kozhevnikov, Cogent Embedded
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*
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* based on nand_spl_simple code
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*
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* (C) Copyright 2006-2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <nand.h>
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#include <asm/io.h>
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#include <linux/mtd/nand_ecc.h>
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static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
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nand_info_t nand_info[1];
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static struct nand_chip nand_chip;
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#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
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CONFIG_SYS_NAND_ECCSIZE)
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#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
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/*
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* NAND command for large page NAND devices (2k)
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*/
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static int nand_command(int block, int page, uint32_t offs,
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u8 cmd)
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{
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struct nand_chip *this = nand_info[0].priv;
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int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
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void (*hwctrl)(struct mtd_info *mtd, int cmd,
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unsigned int ctrl) = this->cmd_ctrl;
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while (!this->dev_ready(&nand_info[0]))
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;
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/* Emulate NAND_CMD_READOOB */
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if (cmd == NAND_CMD_READOOB) {
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offs += CONFIG_SYS_NAND_PAGE_SIZE;
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cmd = NAND_CMD_READ0;
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}
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/* Begin command latch cycle */
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hwctrl(&nand_info[0], cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
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if (cmd == NAND_CMD_RESET) {
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hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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while (!this->dev_ready(&nand_info[0]))
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;
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return 0;
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}
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/* Shift the offset from byte addressing to word addressing. */
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if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
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offs >>= 1;
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/* Set ALE and clear CLE to start address cycle */
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/* Column address */
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hwctrl(&nand_info[0], offs & 0xff,
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NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
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hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
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/* Row address */
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if (cmd != NAND_CMD_RNDOUT) {
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hwctrl(&nand_info[0], (page_addr & 0xff),
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NAND_CTRL_ALE); /* A[19:12] */
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hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
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NAND_CTRL_ALE); /* A[27:20] */
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#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
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/* One more address cycle for devices > 128MiB */
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hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
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NAND_CTRL_ALE); /* A[31:28] */
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#endif
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}
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hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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if (cmd == NAND_CMD_READ0) {
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/* Latch in address */
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hwctrl(&nand_info[0], NAND_CMD_READSTART,
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NAND_CTRL_CLE | NAND_CTRL_CHANGE);
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hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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/*
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* Wait a while for the data to be ready
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*/
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while (!this->dev_ready(&nand_info[0]))
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;
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} else if (cmd == NAND_CMD_RNDOUT) {
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hwctrl(&nand_info[0], NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
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NAND_CTRL_CHANGE);
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hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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}
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return 0;
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}
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static int nand_is_bad_block(int block)
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{
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struct nand_chip *this = nand_info[0].priv;
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nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
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NAND_CMD_READOOB);
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/*
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* Read one byte (or two if it's a 16 bit chip).
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*/
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if (this->options & NAND_BUSWIDTH_16) {
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if (readw(this->IO_ADDR_R) != 0xffff)
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return 1;
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} else {
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if (readb(this->IO_ADDR_R) != 0xff)
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return 1;
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}
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return 0;
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}
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static int nand_read_page(int block, int page, void *dst)
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{
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struct nand_chip *this = nand_info[0].priv;
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u_char ecc_calc[ECCTOTAL];
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u_char ecc_code[ECCTOTAL];
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u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
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int i;
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int eccsize = CONFIG_SYS_NAND_ECCSIZE;
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int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
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int eccsteps = ECCSTEPS;
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uint8_t *p = dst;
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uint32_t data_pos = 0;
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uint8_t *oob = &oob_data[0] + nand_ecc_pos[0];
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uint32_t oob_pos = eccsize * eccsteps + nand_ecc_pos[0];
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nand_command(block, page, 0, NAND_CMD_READ0);
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for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
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this->ecc.hwctl(&nand_info[0], NAND_ECC_READ);
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nand_command(block, page, data_pos, NAND_CMD_RNDOUT);
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this->read_buf(&nand_info[0], p, eccsize);
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nand_command(block, page, oob_pos, NAND_CMD_RNDOUT);
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this->read_buf(&nand_info[0], oob, eccbytes);
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this->ecc.calculate(&nand_info[0], p, &ecc_calc[i]);
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data_pos += eccsize;
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oob_pos += eccbytes;
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oob += eccbytes;
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}
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/* Pick the ECC bytes out of the oob data */
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for (i = 0; i < ECCTOTAL; i++)
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ecc_code[i] = oob_data[nand_ecc_pos[i]];
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eccsteps = ECCSTEPS;
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p = dst;
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for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
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/* No chance to do something with the possible error message
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* from correct_data(). We just hope that all possible errors
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* are corrected by this routine.
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*/
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this->ecc.correct(&nand_info[0], p, &ecc_code[i], &ecc_calc[i]);
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}
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return 0;
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}
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int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
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{
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unsigned int block, lastblock;
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unsigned int page;
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/*
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* offs has to be aligned to a page address!
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*/
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block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
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lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
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page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
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while (block <= lastblock) {
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if (!nand_is_bad_block(block)) {
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/*
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* Skip bad blocks
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*/
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while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
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nand_read_page(block, page, dst);
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dst += CONFIG_SYS_NAND_PAGE_SIZE;
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page++;
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}
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page = 0;
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} else {
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lastblock++;
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}
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block++;
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}
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return 0;
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}
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/* nand_init() - initialize data to make nand usable by SPL */
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void nand_init(void)
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{
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/*
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* Init board specific nand support
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*/
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nand_info[0].priv = &nand_chip;
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nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
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(void __iomem *)CONFIG_SYS_NAND_BASE;
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board_nand_init(&nand_chip);
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if (nand_chip.select_chip)
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nand_chip.select_chip(&nand_info[0], 0);
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/* NAND chip may require reset after power-on */
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nand_command(0, 0, 0, NAND_CMD_RESET);
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}
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/* Unselect after operation */
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void nand_deselect(void)
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{
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if (nand_chip.select_chip)
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nand_chip.select_chip(&nand_info[0], -1);
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}
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