Kever Yang f3f6591ca3 rockchip: rk322x: fix pd_bus hclk/pclk ... The pd_bus hclk/pclk source is pd_bus aclk, not the PLL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>		2017-10-01 00:33:32 +02:00
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clk_rk322x.c	rockchip: rk322x: fix pd_bus hclk/pclk	2017-10-01 00:33:32 +02:00
clk_rk3036.c	rockchip: clk: remove RATE_TO_DIV	2017-08-13 17:15:09 +02:00
clk_rk3188.c	rockchip: clk: remove RATE_TO_DIV	2017-08-13 17:15:09 +02:00
clk_rk3288.c	rockchip: clk: Add SARADC clock support for rk3288	2017-10-01 00:33:29 +02:00
clk_rk3328.c	rockchip: clk: Add rk3328 SARADC clock support	2017-10-01 00:33:30 +02:00
clk_rk3368.c	rockchip: clk: Add rk3368 SARADC clock support	2017-10-01 00:33:30 +02:00
clk_rk3399.c	rockchip: clk: Add rk3399 SARADC clock support	2017-10-01 00:33:30 +02:00
clk_rv1108.c	rockchip: clk: Add rv1108 SARADC clock support	2017-10-01 00:33:29 +02:00
Makefile	rockchip: rk322x: add clock driver	2017-07-11 12:13:45 +02:00