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https://github.com/brain-hackers/u-boot-brain
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d38da53794
The existing code assumes the SDRAM row refresh period should always be 15.6 us. This is not always true, and indeed on the ATNGW100, the refresh rate should really be 7.81 us. Add a refresh_period member to struct sdram_info and initialize it properly for both ATSTK1000 and ATNGW100. Out-of-tree boards will panic() until the refresh_period member is updated properly. Big thanks to Gerhard Berghofer for pointing out this issue. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
37 lines
1.2 KiB
C
37 lines
1.2 KiB
C
/*
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* Copyright (C) 2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_AVR32_SDRAM_H
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#define __ASM_AVR32_SDRAM_H
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struct sdram_info {
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unsigned long phys_addr;
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unsigned int row_bits, col_bits, bank_bits;
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unsigned int cas, twr, trc, trp, trcd, tras, txsr;
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/* SDRAM refresh period in cycles */
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unsigned long refresh_period;
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};
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extern unsigned long sdram_init(const struct sdram_info *info);
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#endif /* __ASM_AVR32_SDRAM_H */
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