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https://github.com/brain-hackers/u-boot-brain
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d38da53794
The existing code assumes the SDRAM row refresh period should always be 15.6 us. This is not always true, and indeed on the ATNGW100, the refresh rate should really be 7.81 us. Add a refresh_period member to struct sdram_info and initialize it properly for both ATSTK1000 and ATNGW100. Out-of-tree boards will panic() until the refresh_period member is updated properly. Big thanks to Gerhard Berghofer for pointing out this issue. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
82 lines
2.2 KiB
C
82 lines
2.2 KiB
C
/*
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* Copyright (C) 2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_AVR32_ARCH_CLK_H__
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#define __ASM_AVR32_ARCH_CLK_H__
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#include <asm/arch/chip-features.h>
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#ifdef CONFIG_PLL
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#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
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#else
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#define MAIN_CLK_RATE (CFG_OSC0_HZ)
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#endif
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static inline unsigned long get_cpu_clk_rate(void)
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{
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return MAIN_CLK_RATE >> CFG_CLKDIV_CPU;
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}
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static inline unsigned long get_hsb_clk_rate(void)
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{
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return MAIN_CLK_RATE >> CFG_CLKDIV_HSB;
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}
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static inline unsigned long get_pba_clk_rate(void)
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{
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return MAIN_CLK_RATE >> CFG_CLKDIV_PBA;
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}
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static inline unsigned long get_pbb_clk_rate(void)
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{
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return MAIN_CLK_RATE >> CFG_CLKDIV_PBB;
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}
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/* Accessors for specific devices. More will be added as needed. */
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static inline unsigned long get_sdram_clk_rate(void)
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{
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return get_hsb_clk_rate();
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}
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#ifdef AT32AP700x_CHIP_HAS_USART
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static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
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{
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return get_pba_clk_rate();
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}
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#endif
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#ifdef AT32AP700x_CHIP_HAS_USART
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static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
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{
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return get_pbb_clk_rate();
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}
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static inline unsigned long get_macb_hclk_rate(unsigned int dev_id)
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{
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return get_hsb_clk_rate();
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}
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#endif
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#ifdef AT32AP700x_CHIP_HAS_MMCI
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static inline unsigned long get_mci_clk_rate(void)
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{
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return get_pbb_clk_rate();
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}
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#endif
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/* Board code may need the SDRAM base clock as a compile-time constant */
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#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB)
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#endif /* __ASM_AVR32_ARCH_CLK_H__ */
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