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https://github.com/brain-hackers/u-boot-brain
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c978b52410
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
56 lines
919 B
C
56 lines
919 B
C
/*
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* Copyright (C) 2016 Cadence Design Systems Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _XTENSA_ATOMIC_H
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#define _XTENSA_ATOMIC_H
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#include <asm/system.h>
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typedef struct { volatile int counter; } atomic_t;
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#define ATOMIC_INIT(i) { (i) }
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#define atomic_read(v) ((v)->counter)
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#define atomic_set(v, i) ((v)->counter = (i))
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static inline void atomic_add(int i, atomic_t *v)
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{
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unsigned long flags;
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local_irq_save(flags);
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v->counter += i;
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local_irq_restore(flags);
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}
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static inline void atomic_sub(int i, atomic_t *v)
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{
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unsigned long flags;
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local_irq_save(flags);
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v->counter -= i;
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local_irq_restore(flags);
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}
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static inline void atomic_inc(atomic_t *v)
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{
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unsigned long flags;
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local_irq_save(flags);
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++v->counter;
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local_irq_restore(flags);
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}
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static inline void atomic_dec(atomic_t *v)
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{
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unsigned long flags;
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local_irq_save(flags);
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--v->counter;
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local_irq_restore(flags);
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}
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#endif
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