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https://github.com/brain-hackers/u-boot-brain
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c978b52410
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
45 lines
854 B
C
45 lines
854 B
C
/*
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* (C) Copyright 2008 - 2013 Tensilica Inc.
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* (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Exception handling.
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* We currently don't handle any exception and force a reset.
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* (Note that alloca is a special case and handled in start.S)
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/string.h>
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#include <asm/regs.h>
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typedef void (*handler_t)(struct pt_regs *);
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void unhandled_exception(struct pt_regs *regs)
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{
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printf("Unhandled Exception: EXCCAUSE = %ld, EXCVADDR = %lx, pc = %lx\n",
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regs->exccause, regs->excvaddr, regs->pc);
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panic("*** PANIC\n");
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}
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handler_t exc_table[EXCCAUSE_LAST] = {
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[0 ... EXCCAUSE_LAST-1] = unhandled_exception,
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};
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int interrupt_init(void)
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{
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return 0;
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}
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void enable_interrupts(void)
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{
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}
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int disable_interrupts(void)
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{
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return 0;
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}
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