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![Wolfgang Denk](/assets/img/avatar_default.png)
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
186 lines
4.6 KiB
C
186 lines
4.6 KiB
C
/*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#include <post.h>
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#include "../common/kup.h"
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#include <asm/io.h>
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#define _NOT_USED_ 0xFFFFFFFF
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const uint sdram_table[] = {
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
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0x1FF77C47, /* last */
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
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/*
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* Burst Read. (Offset 8 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
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0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPMA RAM)
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*/
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0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
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0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPMA RAM)
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*/
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0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC84, 0xFFFFFC07, /* last */
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_NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPMA RAM)
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*/
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0x7FFFFC07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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/*
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* Check Board Identity:
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*/
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int checkboard(void)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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uchar latch, rev, mod;
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/*
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* Init ChipSelect #4 (CAN + HW-Latch)
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*/
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out_be32(&memctl->memc_or4, 0xFFFF8926);
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out_be32(&memctl->memc_br4, 0x90000401);
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latch = in_8( (unsigned char *) LATCH_ADDR);
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rev = (latch & 0xF8) >> 3;
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mod = (latch & 0x03);
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printf("Board: KUP4X Rev %d.%d\n", rev, mod);
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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upmconfig(UPMA, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
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out_be32(&memctl->memc_mar, 0x00000088);
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out_be32(&memctl->memc_mamr,
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CONFIG_SYS_MAMR & (~(MAMR_PTAE))); /* no refresh yet */
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udelay(200);
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/* perform SDRAM initializsation sequence */
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/* SDRAM bank 0 */
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out_be32(&memctl->memc_mcr, 0x80002105);
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udelay(1);
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out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */
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udelay(1);
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out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */
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udelay(1);
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/* SDRAM bank 1 */
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out_be32(&memctl->memc_mcr, 0x80004105);
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udelay(1);
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out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */
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udelay(1);
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out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */
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udelay(1);
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/* SDRAM bank 2 */
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out_be32(&memctl->memc_mcr, 0x80006105);
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udelay(1);
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out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */
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udelay(1);
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out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */
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udelay(1);
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/* SDRAM bank 3 */
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out_be32(&memctl->memc_mcr, 0x8000C105);
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udelay(1);
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out_be32(&memctl->memc_mcr, 0x8000C830); /* execute twice */
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udelay(1);
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out_be32(&memctl->memc_mcr, 0x8000C106); /* RUN MRS Pattern from loc 6 */
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udelay(1);
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setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */
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udelay(1000);
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/* 4 x 16 MB */
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out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
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udelay(1000);
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out_be32(&memctl->memc_or1, 0xFF000A00);
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out_be32(&memctl->memc_br1, 0x00000081);
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out_be32(&memctl->memc_or2, 0xFE000A00);
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out_be32(&memctl->memc_br2, 0x01000081);
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out_be32(&memctl->memc_or3, 0xFD000A00);
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out_be32(&memctl->memc_br3, 0x02000081);
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out_be32(&memctl->memc_or6, 0xFC000A00);
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out_be32(&memctl->memc_br6, 0x03000081);
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udelay(10000);
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return (4 * 16 * 1024 * 1024);
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}
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int misc_init_r(void)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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#ifdef CONFIG_IDE_LED
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/* Configure PA8 as output port */
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setbits_be16(&immap->im_ioport.iop_padir, PA_8);
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setbits_be16(&immap->im_ioport.iop_paodr, PA_8);
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clrbits_be16(&immap->im_ioport.iop_papar, PA_8);
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setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */
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#endif
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load_sernum_ethaddr();
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setenv("hw", "4x");
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poweron_key();
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return 0;
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}
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