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![Heiko Schocher](/assets/img/avatar_default.png)
add support for the ids8313 board. CPU: e300c3, MPC8313, Rev: 2.1 at 396 MHz, CSB: 132 MHz I2C: ready SPI: ready DRAM: 128 MiB (DDR2, 32-bit, ECC off, 264 MHz) Flash: 8 MiB NAND: 128 MiB Net: TSEC0, TSEC1 [PRIME] public key on NOR flash start Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
209 lines
5.0 KiB
C
209 lines
5.0 KiB
C
/*
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* (C) Copyright 2013
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* Based on:
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* Copyright (c) 2011 IDS GmbH, Germany
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* ids8313.c - ids8313 board support.
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*
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* Sergej Stepanov <ste@ids.de>
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* Based on board/freescale/mpc8313erdb/mpc8313erdb.c
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc83xx.h>
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#include <spi.h>
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#include <libfdt.h>
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DECLARE_GLOBAL_DATA_PTR;
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/** CPLD contains the info about:
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* - board type: *pCpld & 0xF0
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* - hw-revision: *pCpld & 0x0F
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* - cpld-revision: *pCpld+1
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*/
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int checkboard(void)
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{
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char *pcpld = (char *)CONFIG_SYS_CPLD_BASE;
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u8 u8Vers = readb(pcpld);
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u8 u8Revs = readb(pcpld + 1);
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printf("Board: ");
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switch (u8Vers & 0xF0) {
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case '\x40':
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printf("CU73X");
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break;
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case '\x50':
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printf("CC73X");
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break;
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default:
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printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs);
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return 0;
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}
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printf("\nInfo: HW-Rev: %i, CPLD-Rev: %i\n",
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u8Vers & 0x0F, u8Revs & 0xFF);
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return 0;
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}
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/*
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* fixed sdram init
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*/
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int fixed_sdram(unsigned long config)
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = CONFIG_SYS_DDR_SIZE << 20;
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#ifndef CONFIG_SYS_RAMBOOT
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u32 msize_log2 = __ilog2(msize);
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out_be32(&im->sysconf.ddrlaw[0].bar,
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(CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
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out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
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out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
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sync();
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/*
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* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
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* or the DDR2 controller may fail to initialize correctly.
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*/
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udelay(50000);
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out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
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out_be32(&im->ddr.cs_config[0], config);
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/* currently we use only one CS, so disable the other banks */
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out_be32(&im->ddr.cs_config[1], 0);
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out_be32(&im->ddr.cs_config[2], 0);
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out_be32(&im->ddr.cs_config[3], 0);
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out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
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out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
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out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
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out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
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out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
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out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
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out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
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out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
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out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
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out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
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sync();
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udelay(300);
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/* enable DDR controller */
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setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
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/* now check the real size */
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disable_addr_trans();
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msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
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enable_addr_trans();
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#endif
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return msize;
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}
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static int setup_sdram(void)
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{
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u32 msize = CONFIG_SYS_DDR_SIZE << 20;
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long int size_01, size_02;
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size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
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size_02 = fixed_sdram(CONFIG_SYS_DDR_CONFIG_256);
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if (size_01 > size_02)
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msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
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else
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msize = size_02;
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return msize;
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}
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phys_size_t initdram(int board_type)
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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fsl_lbc_t *lbc = &im->im_lbc;
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u32 msize = 0;
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if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
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return -1;
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msize = setup_sdram();
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out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
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out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
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sync();
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return msize;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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}
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#endif
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/* gpio mask for spi_cs */
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#define IDSCPLD_SPI_CS_MASK 0x00000001
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/* spi_cs multiplexed through cpld */
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#define IDSCPLD_SPI_CS_BASE (CONFIG_SYS_CPLD_BASE + 0xf)
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#if defined(CONFIG_MISC_INIT_R)
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/* srp umcr mask for rts */
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#define IDSUMCR_RTS_MASK 0x04
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int misc_init_r(void)
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{
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/*srp*/
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duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0];
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duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1];
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gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
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u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
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/* deactivate spi_cs channels */
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out_8(spi_base, 0);
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/* deactivate the spi_cs */
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setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK);
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/*srp - deactivate rts*/
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out_8(&uart1->umcr, IDSUMCR_RTS_MASK);
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out_8(&uart2->umcr, IDSUMCR_RTS_MASK);
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gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE;
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return 0;
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}
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#endif
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#ifdef CONFIG_MPC8XXX_SPI
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/*
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* The following are used to control the SPI chip selects
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*/
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && ((cs >= 0) && (cs <= 2));
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
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u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
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/* select the spi_cs channel */
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out_8(spi_base, 1 << slave->cs);
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/* activate the spi_cs */
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clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
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u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
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/* select the spi_cs channel */
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out_8(spi_base, 1 << slave->cs);
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/* deactivate the spi_cs */
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setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
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}
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#endif /* CONFIG_HARD_SPI */
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