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![Suneel Garapati](/assets/img/avatar_default.png)
Adds support for Network Interface controllers found on OcteonTX2 SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
91 lines
1.6 KiB
C
91 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#ifndef __NPC_H__
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#define __NPC_H__
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#define RSVD_MCAM_ENTRIES_PER_PF 2 /** Ucast and Bcast */
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#define RSVD_MCAM_ENTRIES_PER_NIXLF 1 /** Ucast for VFs */
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struct npc_kpu_profile_cam {
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u8 state;
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u8 state_mask;
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u16 dp0;
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u16 dp0_mask;
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u16 dp1;
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u16 dp1_mask;
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u16 dp2;
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u16 dp2_mask;
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};
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struct npc_kpu_profile_action {
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u8 errlev;
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u8 errcode;
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u8 dp0_offset;
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u8 dp1_offset;
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u8 dp2_offset;
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u8 bypass_count;
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u8 parse_done;
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u8 next_state;
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u8 ptr_advance;
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u8 cap_ena;
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u8 lid;
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u8 ltype;
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u8 flags;
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u8 offset;
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u8 mask;
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u8 right;
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u8 shift;
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};
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struct npc_kpu_profile {
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int cam_entries;
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int action_entries;
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struct npc_kpu_profile_cam *cam;
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struct npc_kpu_profile_action *action;
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};
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struct npc_pkind {
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struct rsrc_bmap rsrc;
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u32 *pfchan_map;
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};
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struct npc_mcam {
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struct rsrc_bmap rsrc;
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u16 *pfvf_map;
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u16 total_entries; /* Total number of MCAM entries */
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u16 entries; /* Total - reserved for NIX LFs */
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u8 banks_per_entry; /* Number of keywords in key */
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u8 keysize;
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u8 banks; /* Number of MCAM banks */
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u16 banksize; /* Number of MCAM entries in each bank */
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u16 counters; /* Number of match counters */
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u16 nixlf_offset;
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u16 pf_offset;
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};
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struct nix_af_handle;
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struct nix_handle;
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struct rvu_hwinfo;
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struct npc_af {
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struct nix_af_handle *nix_af;
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struct npc_pkind pkind;
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void __iomem *npc_af_base;
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u8 npc_kpus; /** Number of parser units */
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struct npc_mcam mcam;
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struct rvu_block block;
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struct rvu_hwinfo *hw;
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};
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struct npc {
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struct npc_af *npc_af;
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void __iomem *npc_base;
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struct nix_handle *nix;
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}
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#endif /* __NPC_H__ */
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