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![Suneel Garapati](/assets/img/avatar_default.png)
Adds support for Network Interface controllers found on OcteonTX2 SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
449 lines
11 KiB
C
449 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#ifndef __CGX_INTF_H__
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#define __CGX_INTF_H__
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#define CGX_FIRMWARE_MAJOR_VER 1
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#define CGX_FIRMWARE_MINOR_VER 0
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/* Register offsets */
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#define CGX_CMR_INT 0x87e0e0000040
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#define CGX_CMR_SCRATCH0 0x87e0e0001050
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#define CGX_CMR_SCRATCH1 0x87e0e0001058
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#define CGX_SHIFT(x) (0x1000000 * ((x) & 0x3))
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#define CMR_SHIFT(x) (0x40000 * ((x) & 0x3))
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/* CGX error types. set for cmd response status as CGX_STAT_FAIL */
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enum cgx_error_type {
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CGX_ERR_NONE,
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CGX_ERR_LMAC_NOT_ENABLED,
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CGX_ERR_LMAC_MODE_INVALID,
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CGX_ERR_REQUEST_ID_INVALID,
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CGX_ERR_PREV_ACK_NOT_CLEAR,
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CGX_ERR_PHY_LINK_DOWN,
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CGX_ERR_PCS_RESET_FAIL,
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CGX_ERR_AN_CPT_FAIL,
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CGX_ERR_TX_NOT_IDLE,
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CGX_ERR_RX_NOT_IDLE,
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CGX_ERR_SPUX_BR_BLKLOCK_FAIL,
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CGX_ERR_SPUX_RX_ALIGN_FAIL,
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CGX_ERR_SPUX_TX_FAULT,
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CGX_ERR_SPUX_RX_FAULT,
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CGX_ERR_SPUX_RESET_FAIL,
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CGX_ERR_SPUX_AN_RESET_FAIL,
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CGX_ERR_SPUX_USX_AN_RESET_FAIL,
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CGX_ERR_SMUX_RX_LINK_NOT_OK,
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CGX_ERR_PCS_LINK_FAIL,
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CGX_ERR_TRAINING_FAIL,
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CGX_ERR_RX_EQU_FAIL,
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CGX_ERR_SPUX_BER_FAIL,
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CGX_ERR_SPUX_RSFEC_ALGN_FAIL,
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CGX_ERR_SPUX_MARKER_LOCK_FAIL,
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CGX_ERR_SET_FEC_INVALID,
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CGX_ERR_SET_FEC_FAIL,
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CGX_ERR_MODULE_INVALID,
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CGX_ERR_MODULE_NOT_PRESENT,
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CGX_ERR_SPEED_CHANGE_INVALID, /* = 28 */
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/* FIXME : add more error types when adding support for new modes */
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};
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/* LINK speed types */
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enum cgx_link_speed {
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CGX_LINK_NONE,
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CGX_LINK_10M,
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CGX_LINK_100M,
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CGX_LINK_1G,
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CGX_LINK_2HG, /* 2.5 Gbps */
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CGX_LINK_5G,
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CGX_LINK_10G,
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CGX_LINK_20G,
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CGX_LINK_25G,
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CGX_LINK_40G,
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CGX_LINK_50G,
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CGX_LINK_80G,
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CGX_LINK_100G,
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CGX_LINK_MAX,
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};
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/* REQUEST ID types. Input to firmware */
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enum cgx_cmd_id {
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CGX_CMD_NONE = 0,
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CGX_CMD_GET_FW_VER,
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CGX_CMD_GET_MAC_ADDR,
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CGX_CMD_SET_MTU,
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CGX_CMD_GET_LINK_STS, /* optional to user */
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CGX_CMD_LINK_BRING_UP, /* = 5 */
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CGX_CMD_LINK_BRING_DOWN,
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CGX_CMD_INTERNAL_LBK,
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CGX_CMD_EXTERNAL_LBK,
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CGX_CMD_HIGIG,
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CGX_CMD_LINK_STAT_CHANGE, /* = 10 */
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CGX_CMD_MODE_CHANGE, /* hot plug support */
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CGX_CMD_INTF_SHUTDOWN,
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CGX_CMD_GET_MKEX_SIZE,
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CGX_CMD_GET_MKEX_PROFILE,
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CGX_CMD_GET_FWD_BASE, /* get base address of shared FW data */
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CGX_CMD_GET_LINK_MODES, /* Supported Link Modes */
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CGX_CMD_SET_LINK_MODE,
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CGX_CMD_GET_SUPPORTED_FEC,
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CGX_CMD_SET_FEC,
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CGX_CMD_GET_AN, /* = 20 */
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CGX_CMD_SET_AN,
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CGX_CMD_GET_ADV_LINK_MODES,
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CGX_CMD_GET_ADV_FEC,
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CGX_CMD_GET_PHY_MOD_TYPE, /* line-side modulation type: NRZ or PAM4 */
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CGX_CMD_SET_PHY_MOD_TYPE, /* = 25 */
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CGX_CMD_PRBS,
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CGX_CMD_DISPLAY_EYE,
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CGX_CMD_GET_PHY_FEC_STATS,
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CGX_CMD_DISPLAY_SERDES,
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CGX_CMD_AN_LOOPBACK, /* = 30 */
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CGX_CMD_GET_PERSIST_IGNORE,
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CGX_CMD_SET_PERSIST_IGNORE,
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CGX_CMD_SET_MAC_ADDR,
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};
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/* async event ids */
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enum cgx_evt_id {
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CGX_EVT_NONE,
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CGX_EVT_LINK_CHANGE,
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};
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/* event types - cause of interrupt */
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enum cgx_evt_type {
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CGX_EVT_ASYNC,
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CGX_EVT_CMD_RESP
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};
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enum cgx_stat {
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CGX_STAT_SUCCESS,
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CGX_STAT_FAIL
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};
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enum cgx_cmd_own {
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/* default ownership with kernel/uefi/u-boot */
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CGX_OWN_NON_SECURE_SW,
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/* set by kernel/uefi/u-boot after posting a new request to ATF */
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CGX_OWN_FIRMWARE,
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};
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/* Supported LINK MODE enums
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* Each link mode is a bit mask of these
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* enums which are represented as bits
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*/
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enum cgx_mode_t {
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CGX_MODE_SGMII_BIT = 0,
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CGX_MODE_1000_BASEX_BIT,
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CGX_MODE_QSGMII_BIT,
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CGX_MODE_10G_C2C_BIT,
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CGX_MODE_10G_C2M_BIT,
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CGX_MODE_10G_KR_BIT,
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CGX_MODE_20G_C2C_BIT,
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CGX_MODE_25G_C2C_BIT,
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CGX_MODE_25G_C2M_BIT,
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CGX_MODE_25G_2_C2C_BIT,
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CGX_MODE_25G_CR_BIT,
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CGX_MODE_25G_KR_BIT,
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CGX_MODE_40G_C2C_BIT,
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CGX_MODE_40G_C2M_BIT,
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CGX_MODE_40G_CR4_BIT,
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CGX_MODE_40G_KR4_BIT,
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CGX_MODE_40GAUI_C2C_BIT,
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CGX_MODE_50G_C2C_BIT,
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CGX_MODE_50G_C2M_BIT,
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CGX_MODE_50G_4_C2C_BIT,
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CGX_MODE_50G_CR_BIT,
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CGX_MODE_50G_KR_BIT,
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CGX_MODE_80GAUI_C2C_BIT,
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CGX_MODE_100G_C2C_BIT,
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CGX_MODE_100G_C2M_BIT,
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CGX_MODE_100G_CR4_BIT,
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CGX_MODE_100G_KR4_BIT,
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CGX_MODE_MAX_BIT /* = 29 */
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};
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/* scratchx(0) CSR used for ATF->non-secure SW communication.
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* This acts as the status register
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* Provides details on command ack/status, link status, error details
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*/
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/* CAUTION : below structures are placed in order based on the bit positions
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* For any updates/new bitfields, corresponding structures needs to be updated
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*/
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struct cgx_evt_sts_s { /* start from bit 0 */
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u64 ack:1;
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u64 evt_type:1; /* cgx_evt_type */
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u64 stat:1; /* cgx_stat */
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u64 id:6; /* cgx_evt_id/cgx_cmd_id */
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u64 reserved:55;
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};
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/* all the below structures are in the same memory location of SCRATCHX(0)
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* value can be read/written based on command ID
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*/
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/* Resp to command IDs with command status as CGX_STAT_FAIL
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* Not applicable for commands :
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* CGX_CMD_LINK_BRING_UP/DOWN/CGX_EVT_LINK_CHANGE
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* check struct cgx_lnk_sts_s comments
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*/
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struct cgx_err_sts_s { /* start from bit 9 */
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u64 reserved1:9;
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u64 type:10; /* cgx_error_type */
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u64 reserved2:35;
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};
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/* Resp to cmd ID as CGX_CMD_GET_FW_VER with cmd status as CGX_STAT_SUCCESS */
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struct cgx_ver_s { /* start from bit 9 */
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u64 reserved1:9;
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u64 major_ver:4;
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u64 minor_ver:4;
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u64 reserved2:47;
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};
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/* Resp to cmd ID as CGX_CMD_GET_MAC_ADDR with cmd status as CGX_STAT_SUCCESS
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* Returns each byte of MAC address in a separate bit field
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*/
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struct cgx_mac_addr_s { /* start from bit 9 */
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u64 reserved1:9;
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u64 addr_0:8;
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u64 addr_1:8;
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u64 addr_2:8;
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u64 addr_3:8;
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u64 addr_4:8;
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u64 addr_5:8;
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u64 reserved2:7;
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};
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/* Resp to cmd ID - CGX_CMD_LINK_BRING_UP/DOWN, event ID CGX_EVT_LINK_CHANGE
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* status can be either CGX_STAT_FAIL or CGX_STAT_SUCCESS
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* In case of CGX_STAT_FAIL, it indicates CGX configuration failed when
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* processing link up/down/change command. Both err_type and current link status
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* will be updated
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* In case of CGX_STAT_SUCCESS, err_type will be CGX_ERR_NONE and current
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* link status will be updated
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*/
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struct cgx_lnk_sts_s {
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u64 reserved1:9;
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u64 link_up:1;
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u64 full_duplex:1;
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u64 speed:4; /* cgx_link_speed */
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u64 err_type:10;
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u64 an:1; /* Current AN state : enabled/disabled */
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u64 fec:2; /* Current FEC type if enabled, if not 0 */
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u64 port:8; /* Share the current port info if required */
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u64 mode:8; /* cgx_mode_t enum integer value */
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u64 reserved2:20;
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};
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struct sh_fwd_base_s {
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u64 reserved1:9;
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u64 addr:55;
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};
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struct cgx_link_modes_s {
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u64 reserved1:9;
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u64 modes:55;
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};
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/* Resp to cmd ID - CGX_CMD_GET_ADV_FEC/CGX_CMD_GET_SUPPORTED_FEC
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* fec : 2 bits
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* typedef enum cgx_fec_type {
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* CGX_FEC_NONE,
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* CGX_FEC_BASE_R,
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* CGX_FEC_RS
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* } fec_type_t;
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*/
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struct cgx_fec_types_s {
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u64 reserved1:9;
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u64 fec:2;
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u64 reserved2:53;
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};
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/* Resp to cmd ID - CGX_CMD_GET_AN */
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struct cgx_get_an_s {
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u64 reserved1:9;
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u64 an:1;
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u64 reserved2:54;
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};
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/* Resp to cmd ID - CGX_CMD_GET_PHY_MOD_TYPE */
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struct cgx_get_phy_mod_type_s {
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u64 reserved1:9;
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u64 mod:1; /* 0=NRZ, 1=PAM4 */
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u64 reserved2:54;
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};
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/* Resp to cmd ID - CGX_CMD_GET_PERSIST_IGNORE */
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struct cgx_get_flash_ignore_s {
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uint64_t reserved1:9;
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uint64_t ignore:1;
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uint64_t reserved2:54;
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};
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union cgx_rsp_sts {
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/* Fixed, applicable for all commands/events */
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struct cgx_evt_sts_s evt_sts;
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/* response to CGX_CMD_LINK_BRINGUP/DOWN/LINK_CHANGE */
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struct cgx_lnk_sts_s link_sts;
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/* response to CGX_CMD_GET_FW_VER */
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struct cgx_ver_s ver;
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/* response to CGX_CMD_GET_MAC_ADDR */
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struct cgx_mac_addr_s mac_s;
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/* response to CGX_CMD_GET_FWD_BASE */
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struct sh_fwd_base_s fwd_base_s;
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/* response if evt_status = CMD_FAIL */
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struct cgx_err_sts_s err;
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/* response to CGX_CMD_GET_SUPPORTED_FEC */
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struct cgx_fec_types_s supported_fec;
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/* response to CGX_CMD_GET_LINK_MODES */
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struct cgx_link_modes_s supported_modes;
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/* response to CGX_CMD_GET_ADV_LINK_MODES */
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struct cgx_link_modes_s adv_modes;
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/* response to CGX_CMD_GET_ADV_FEC */
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struct cgx_fec_types_s adv_fec;
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/* response to CGX_CMD_GET_AN */
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struct cgx_get_an_s an;
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/* response to CGX_CMD_GET_PHY_MOD_TYPE */
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struct cgx_get_phy_mod_type_s phy_mod_type;
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/* response to CGX_CMD_GET_PERSIST_IGNORE */
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struct cgx_get_flash_ignore_s persist;
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#ifdef NT_FW_CONFIG
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/* response to CGX_CMD_GET_MKEX_SIZE */
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struct cgx_mcam_profile_sz_s prfl_sz;
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/* response to CGX_CMD_GET_MKEX_PROFILE */
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struct cgx_mcam_profile_addr_s prfl_addr;
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#endif
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};
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union cgx_scratchx0 {
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u64 u;
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union cgx_rsp_sts s;
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};
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/* scratchx(1) CSR used for non-secure SW->ATF communication
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* This CSR acts as a command register
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*/
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struct cgx_cmd { /* start from bit 2 */
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u64 reserved1:2;
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u64 id:6; /* cgx_request_id */
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u64 reserved2:56;
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};
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/* all the below structures are in the same memory location of SCRATCHX(1)
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* corresponding arguments for command Id needs to be updated
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*/
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/* Any command using enable/disable as an argument need
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* to pass the option via this structure.
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* Ex: Loopback, HiGig...
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*/
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struct cgx_ctl_args { /* start from bit 8 */
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u64 reserved1:8;
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u64 enable:1;
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u64 reserved2:55;
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};
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/* command argument to be passed for cmd ID - CGX_CMD_SET_MTU */
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struct cgx_mtu_args {
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u64 reserved1:8;
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u64 size:16;
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u64 reserved2:40;
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};
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/* command argument to be passed for cmd ID - CGX_CMD_MODE_CHANGE */
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struct cgx_mode_change_args {
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uint64_t reserved1:8;
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uint64_t speed:4; /* cgx_link_speed enum */
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uint64_t duplex:1; /* 0 - full duplex, 1 - half duplex */
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uint64_t an:1; /* 0 - disable AN, 1 - enable AN */
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uint64_t port:8; /* device port */
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uint64_t mode:42;
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};
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/* command argument to be passed for cmd ID - CGX_CMD_LINK_CHANGE */
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struct cgx_link_change_args { /* start from bit 8 */
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u64 reserved1:8;
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u64 link_up:1;
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u64 full_duplex:1;
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u64 speed:4; /* cgx_link_speed */
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u64 reserved2:50;
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};
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/* command argument to be passed for cmd ID - CGX_CMD_SET_LINK_MODE */
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struct cgx_set_mode_args {
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u64 reserved1:8;
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u64 mode:56;
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};
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/* command argument to be passed for cmd ID - CGX_CMD_SET_FEC */
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struct cgx_set_fec_args {
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u64 reserved1:8;
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u64 fec:2;
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u64 reserved2:54;
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};
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/* command argument to be passed for cmd ID - CGX_CMD_SET_PHY_MOD_TYPE */
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struct cgx_set_phy_mod_args {
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u64 reserved1:8;
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u64 mod:1; /* 0=NRZ, 1=PAM4 */
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u64 reserved2:55;
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};
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/* command argument to be passed for cmd ID - CGX_CMD_SET_PERSIST_IGNORE */
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struct cgx_set_flash_ignore_args {
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uint64_t reserved1:8;
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uint64_t ignore:1;
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uint64_t reserved2:55;
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};
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/* command argument to be passed for cmd ID - CGX_CMD_SET_MAC_ADDR */
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struct cgx_mac_addr_args {
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uint64_t reserved1:8;
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uint64_t addr:48;
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uint64_t pf_id:8;
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};
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struct cgx_prbs_args {
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u64 reserved1:8; /* start from bit 8 */
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u64 lane:8;
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u64 qlm:8;
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u64 stop_on_error:1;
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u64 mode:8;
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u64 time:31;
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};
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struct cgx_display_eye_args {
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u64 reserved1:8; /* start from bit 8 */
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u64 qlm:8;
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u64 lane:47;
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};
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union cgx_cmd_s {
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u64 own_status:2; /* cgx_cmd_own */
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struct cgx_cmd cmd;
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struct cgx_ctl_args cmd_args;
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struct cgx_mtu_args mtu_size;
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struct cgx_link_change_args lnk_args; /* Input to CGX_CMD_LINK_CHANGE */
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struct cgx_set_mode_args mode_args;
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struct cgx_mode_change_args mode_change_args;
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struct cgx_set_fec_args fec_args;
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struct cgx_set_phy_mod_args phy_mod_args;
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struct cgx_set_flash_ignore_args persist_args;
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struct cgx_mac_addr_args mac_args;
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/* any other arg for command id * like : mtu, dmac filtering control */
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struct cgx_prbs_args prbs_args;
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struct cgx_display_eye_args dsp_eye_args;
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};
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union cgx_scratchx1 {
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u64 u;
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union cgx_cmd_s s;
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};
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#endif /* __CGX_INTF_H__ */
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