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b375d84135
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 10-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
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clk_rk322x.c | ||
clk_rk3036.c | ||
clk_rk3188.c | ||
clk_rk3288.c | ||
clk_rk3328.c | ||
clk_rk3368.c | ||
clk_rk3399.c | ||
clk_rv1108.c | ||
Makefile |