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39245c8699
Based on the definitive guide to EMIF configuration[1] certain registers that we have been modifying (and are documented registers) should be left in their reset values rather than modified. This has been tested on AM335x GP EVM and Beaglebone White. [1]: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Javier Martinez Canillas <javier@dowhile0.org> Cc: Heiko Schocher <hs@denx.de> Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Tom Rini <trini@ti.com> Tested-by: Matt Porter <matt.porter@linaro.org>
107 lines
2.7 KiB
C
107 lines
2.7 KiB
C
/*
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* SPL specific code for Compulab CM-T335 board
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*
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* Board functions for Compulab CM-T335 board
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*
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* Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
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*
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* Author: Ilya Ledvich <ilya@compulab.co.il>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clocks_am33xx.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware_am33xx.h>
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#include <asm/sizes.h>
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = MT41J128MJT125_RD_DQS,
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.datawdsratio0 = MT41J128MJT125_WR_DQS,
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.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
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.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = MT41J128MJT125_RATIO,
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.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
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.cmd1csratio = MT41J128MJT125_RATIO,
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.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
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.cmd2csratio = MT41J128MJT125_RATIO,
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.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = MT41J128MJT125_EMIF_SDCFG,
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.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
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.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
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.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
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.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
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.zq_config = MT41J128MJT125_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
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PHY_EN_DYN_PWRDN,
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};
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const struct dpll_params dpll_ddr = {
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/* M N M2 M3 M4 M5 M6 */
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303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1};
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void am33xx_spl_board_init(void)
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{
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struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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/* Get the frequency */
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dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
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/* Set CORE Frequencies to OPP100 */
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do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
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/* Set MPU Frequency to what we detected now that voltages are set */
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do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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return &dpll_ddr;
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}
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static void probe_sdram_size(long size)
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{
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switch (size) {
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case SZ_512M:
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ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG;
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break;
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case SZ_256M:
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ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG;
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break;
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case SZ_128M:
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ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG;
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break;
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default:
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puts("Failed configuring DRAM, resetting...\n\n");
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reset_cpu(0);
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}
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debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
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config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
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&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
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}
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void sdram_init(void)
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{
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long size = SZ_1G;
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do {
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size = size / 2;
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probe_sdram_size(size);
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} while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size);
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return;
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}
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