Eric Nelson b33f74ead4 mx6: ddr: allow 32 cycles for DQS gating calibration ... The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample cycle) for the first PHY. Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0 output value isn't polluted with calibration artifacts. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Marek Vasut <marex@denx.de>		2016-11-29 16:39:58 +01:00
..
clock.c	imx: mx6sx: Disable ENET clock before switching clock parent	2016-11-16 20:53:55 +01:00
ddr.c	mx6: ddr: allow 32 cycles for DQS gating calibration	2016-11-29 16:39:58 +01:00
Kconfig	engicam: icorem6: Add DM_GPIO, DM_MMC support	2016-10-26 16:53:16 +02:00
Makefile	imx: hab: rework secure boot support for imx6	2015-10-30 15:20:57 +01:00
mp.c	treewide: replace #include <asm/errno.h> with <linux/errno.h>	2016-09-23 17:55:42 -04:00
soc.c	imx: mx6ull: update the REFTOP_VBGADJ setting	2016-11-16 20:53:55 +01:00