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https://github.com/brain-hackers/u-boot-brain
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
39 lines
1.2 KiB
C
39 lines
1.2 KiB
C
/*
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* (C) Copyright 2011
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Lei Wen <leiwen@marvell.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _PANTHEON_H
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#define _PANTHEON_H
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/* Common APB clock register bit definitions */
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#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
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#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
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#define APBC_RST (1<<2) /* Reset Generation */
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/* Functional Clock Selection Mask */
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#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
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/* Common APMU register bit definitions */
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#define APMU_PERI_CLK (1<<4) /* Peripheral Clock Enable */
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#define APMU_AXI_CLK (1<<3) /* AXI Clock Enable*/
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#define APMU_PERI_RST (1<<1) /* Peripheral Reset */
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#define APMU_AXI_RST (1<<0) /* AXI Reset */
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/* Register Base Addresses */
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#define PANTHEON_DRAM_BASE 0xB0000000
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#define PANTHEON_TIMER_BASE 0xD4014000
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#define PANTHEON_WD_TIMER_BASE 0xD4080000
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#define PANTHEON_APBC_BASE 0xD4015000
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#define PANTHEON_UART1_BASE 0xD4017000
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#define PANTHEON_UART2_BASE 0xD4018000
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#define PANTHEON_GPIO_BASE 0xD4019000
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#define PANTHEON_MFPR_BASE 0xD401E000
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#define PANTHEON_MPMU_BASE 0xD4050000
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#define PANTHEON_APMU_BASE 0xD4282800
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#define PANTHEON_CPU_BASE 0xD4282C00
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#endif /* _PANTHEON_H */
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