mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-30 13:58:51 +09:00
989ce04999
Add bcm281xx architecture support code including a clock framework and chip reset. Define register block base addresses for the bcm281xx architecture and create an empty gpio header file required when CONFIG_CMD_GPIO is set. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Steve Rae <srae@broadcom.com> Reviewed-by: Tim Kryger <tkryger@linaro.org>
26 lines
685 B
C
26 lines
685 B
C
/*
|
|
* Copyright 2013 Broadcom Corporation.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#ifndef __ARCH_BCM281XX_SYSMAP_H
|
|
|
|
#define BSC1_BASE_ADDR 0x3e016000
|
|
#define BSC2_BASE_ADDR 0x3e017000
|
|
#define BSC3_BASE_ADDR 0x3e018000
|
|
#define GPIO2_BASE_ADDR 0x35003000
|
|
#define KONA_MST_CLK_BASE_ADDR 0x3f001000
|
|
#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
|
|
#define PMU_BSC_BASE_ADDR 0x3500d000
|
|
#define PWRMGR_BASE_ADDR 0x35010000
|
|
#define SDIO1_BASE_ADDR 0x3f180000
|
|
#define SDIO2_BASE_ADDR 0x3f190000
|
|
#define SDIO3_BASE_ADDR 0x3f1a0000
|
|
#define SDIO4_BASE_ADDR 0x3f1b0000
|
|
#define SECWD_BASE_ADDR 0x3500c000
|
|
#define SECWD2_BASE_ADDR 0x35002f40
|
|
#define TIMER_BASE_ADDR 0x3e00d000
|
|
|
|
#endif
|