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b339b5dbca
The function is very specific to the rk3288 in its arguments referencing the rk3288 cru and grf and every other rockchip soc has differing cru and grf registers. So make that function naming explicit. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
71 lines
1.3 KiB
C
71 lines
1.3 KiB
C
/*
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* (C) Copyright 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ASM_ARCH_CLOCK_H
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#define _ASM_ARCH_CLOCK_H
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/* define pll mode */
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#define RKCLK_PLL_MODE_SLOW 0
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#define RKCLK_PLL_MODE_NORMAL 1
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enum {
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ROCKCHIP_SYSCON_NOC,
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ROCKCHIP_SYSCON_GRF,
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ROCKCHIP_SYSCON_SGRF,
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ROCKCHIP_SYSCON_PMU,
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};
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/* Standard Rockchip clock numbers */
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enum rk_clk_id {
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CLK_OSC,
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CLK_ARM,
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CLK_DDR,
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CLK_CODEC,
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CLK_GENERAL,
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CLK_NEW,
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CLK_COUNT,
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};
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static inline int rk_pll_id(enum rk_clk_id clk_id)
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{
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return clk_id - 1;
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}
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/**
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* clk_get_divisor() - Calculate the required clock divisior
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*
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* Given an input rate and a required output_rate, calculate the Rockchip
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* divisor needed to achieve this.
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*
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* @input_rate: Input clock rate in Hz
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* @output_rate: Output clock rate in Hz
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* @return divisor register value to use
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*/
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static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
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{
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uint clk_div;
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clk_div = input_rate / output_rate;
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clk_div = (clk_div + 1) & 0xfffe;
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return clk_div;
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}
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/**
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* rockchip_get_cru() - get a pointer to the clock/reset unit registers
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*
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* @return pointer to registers, or -ve error on error
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*/
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void *rockchip_get_cru(void);
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struct rk3288_cru;
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struct rk3288_grf;
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void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
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#endif
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