mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 10:46:15 +09:00
2c2b218383
This patch makes the 2nd DRAM bank available on Juno only and not on
other vexpress64 targets, eg. the FVP models.
The commit below added a 2nd bank of NOR flash for Juno, but also for
all vexpress64 targets:
commit 2d0cee1ca2
Author: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Date: Mon Oct 19 11:08:31 2015 +0100
vexpress64: Juno: Declare all 8GB of RAM and make them visible to the kernel.
Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
Declare a secondary memory bank and set the sizes correctly.
Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Unfortunately, I only fully tested on Juno R0, R1 and the FVP Foundation
model. Whilst FVP Base AEMV8 models run U-Boot OK, they fail to boot
the kernel.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Acked-by: Liviu Dudau <liviu.dudau@foss.arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
81 lines
1.5 KiB
C
81 lines
1.5 KiB
C
/*
|
|
* (C) Copyright 2013
|
|
* David Feng <fenghua@phytium.com.cn>
|
|
* Sharma Bhupesh <bhupesh.sharma@freescale.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
#include <common.h>
|
|
#include <malloc.h>
|
|
#include <errno.h>
|
|
#include <netdev.h>
|
|
#include <asm/io.h>
|
|
#include <linux/compiler.h>
|
|
#include <dm/platdata.h>
|
|
#include <dm/platform_data/serial_pl01x.h>
|
|
#include "pcie.h"
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
static const struct pl01x_serial_platdata serial_platdata = {
|
|
.base = V2M_UART0,
|
|
.type = TYPE_PL011,
|
|
.clock = CONFIG_PL011_CLOCK,
|
|
};
|
|
|
|
U_BOOT_DEVICE(vexpress_serials) = {
|
|
.name = "serial_pl01x",
|
|
.platdata = &serial_platdata,
|
|
};
|
|
|
|
/* This function gets replaced by platforms supporting PCIe.
|
|
* The replacement function, eg. on Juno, initialises the PCIe bus.
|
|
*/
|
|
__weak void vexpress64_pcie_init(void)
|
|
{
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
vexpress64_pcie_init();
|
|
return 0;
|
|
}
|
|
|
|
int dram_init(void)
|
|
{
|
|
gd->ram_size = PHYS_SDRAM_1_SIZE;
|
|
return 0;
|
|
}
|
|
|
|
void dram_init_banksize(void)
|
|
{
|
|
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
|
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
|
#ifdef PHYS_SDRAM_2
|
|
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
|
|
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Board specific reset that is system reset.
|
|
*/
|
|
void reset_cpu(ulong addr)
|
|
{
|
|
}
|
|
|
|
/*
|
|
* Board specific ethernet initialization routine.
|
|
*/
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
int rc = 0;
|
|
#ifdef CONFIG_SMC91111
|
|
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
|
|
#endif
|
|
#ifdef CONFIG_SMC911X
|
|
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
|
|
#endif
|
|
return rc;
|
|
}
|