mirror of
https://github.com/brain-hackers/u-boot-brain
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6238935d01
A mailbox is a hardware mechanism for transferring small message and/or notifications between the CPU on which U-Boot runs and some other device such as an auxilliary CPU running firmware or a hardware module. This patch defines a standard API that connects mailbox clients to mailbox providers (drivers). Initially, DT is the only supported method for connecting the two. The DT binding specification (mailbox.txt) was taken from Linux kernel v4.5's Documentation/devicetree/bindings/mailbox/mailbox.txt. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
89 lines
3.2 KiB
C
89 lines
3.2 KiB
C
/*
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* Copyright (c) 2013 Google, Inc
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*
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* (C) Copyright 2012
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* Pavel Herrmann <morpheus.ibis@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _DM_UCLASS_ID_H
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#define _DM_UCLASS_ID_H
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/* TODO(sjg@chromium.org): this could be compile-time generated */
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enum uclass_id {
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/* These are used internally by driver model */
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UCLASS_ROOT = 0,
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UCLASS_DEMO,
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UCLASS_TEST,
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UCLASS_TEST_FDT,
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UCLASS_TEST_BUS,
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UCLASS_SPI_EMUL, /* sandbox SPI device emulator */
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UCLASS_I2C_EMUL, /* sandbox I2C device emulator */
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UCLASS_PCI_EMUL, /* sandbox PCI device emulator */
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UCLASS_USB_EMUL, /* sandbox USB bus device emulator */
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UCLASS_SIMPLE_BUS, /* bus with child devices */
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/* U-Boot uclasses start here - in alphabetical order */
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UCLASS_ADC, /* Analog-to-digital converter */
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UCLASS_AHCI, /* SATA disk controller */
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UCLASS_BLK, /* Block device */
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UCLASS_CLK, /* Clock source, e.g. used by peripherals */
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UCLASS_CPU, /* CPU, typically part of an SoC */
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UCLASS_CROS_EC, /* Chrome OS EC */
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UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */
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UCLASS_DMA, /* Direct Memory Access */
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UCLASS_RAM, /* RAM controller */
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UCLASS_ETH, /* Ethernet device */
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UCLASS_GPIO, /* Bank of general-purpose I/O pins */
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UCLASS_I2C, /* I2C bus */
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UCLASS_I2C_EEPROM, /* I2C EEPROM device */
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UCLASS_I2C_GENERIC, /* Generic I2C device */
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UCLASS_I2C_MUX, /* I2C multiplexer */
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UCLASS_IRQ, /* Interrupt controller */
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UCLASS_KEYBOARD, /* Keyboard input device */
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UCLASS_LED, /* Light-emitting diode (LED) */
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UCLASS_LPC, /* x86 'low pin count' interface */
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UCLASS_MAILBOX, /* Mailbox controller */
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UCLASS_MASS_STORAGE, /* Mass storage device */
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UCLASS_MISC, /* Miscellaneous device */
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UCLASS_MMC, /* SD / MMC card or chip */
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UCLASS_MOD_EXP, /* RSA Mod Exp device */
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UCLASS_MTD, /* Memory Technology Device (MTD) device */
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UCLASS_NORTHBRIDGE, /* Intel Northbridge / SDRAM controller */
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UCLASS_PANEL, /* Display panel, such as an LCD */
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UCLASS_PANEL_BACKLIGHT, /* Backlight controller for panel */
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UCLASS_PCH, /* x86 platform controller hub */
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UCLASS_PCI, /* PCI bus */
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UCLASS_PCI_GENERIC, /* Generic PCI bus device */
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UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */
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UCLASS_PINCONFIG, /* Pin configuration node device */
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UCLASS_PMIC, /* PMIC I/O device */
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UCLASS_PWM, /* Pulse-width modulator */
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UCLASS_PWRSEQ, /* Power sequence device */
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UCLASS_REGULATOR, /* Regulator device */
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UCLASS_REMOTEPROC, /* Remote Processor device */
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UCLASS_RTC, /* Real time clock device */
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UCLASS_SERIAL, /* Serial UART */
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UCLASS_SPI, /* SPI bus */
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UCLASS_SPMI, /* System Power Management Interface bus */
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UCLASS_SPI_FLASH, /* SPI flash */
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UCLASS_SPI_GENERIC, /* Generic SPI flash target */
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UCLASS_SYSCON, /* System configuration device */
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UCLASS_SYSRESET, /* System reset device */
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UCLASS_THERMAL, /* Thermal sensor */
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UCLASS_TIMER, /* Timer device */
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UCLASS_TPM, /* Trusted Platform Module TIS interface */
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UCLASS_USB, /* USB bus */
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UCLASS_USB_DEV_GENERIC, /* USB generic device */
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UCLASS_USB_HUB, /* USB hub */
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UCLASS_VIDEO, /* Video or LCD device */
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UCLASS_VIDEO_BRIDGE, /* Video bridge, e.g. DisplayPort to LVDS */
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UCLASS_VIDEO_CONSOLE, /* Text console driver for video device */
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UCLASS_COUNT,
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UCLASS_INVALID = -1,
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};
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#endif
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