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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-23 02:18:51 +09:00
![Maxime Ripard](/assets/img/avatar_default.png)
All the new SoCs from Allwinner since the A33 have had the phy_ctl offset at 0x410 instead of 0x404 that was used on the previous SoCs. Instead of adding more and more special cases as the number of SoCs grow, let's invert the test to have 0x410 by default, and the (hopefully) fixed number of old SoCs being the exception. Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Suggested-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
408 lines
8.9 KiB
C
408 lines
8.9 KiB
C
/*
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* Sunxi usb-phy code
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*
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* Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
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* Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
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*
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* Based on code from
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/usb_phy.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <errno.h>
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#if defined(CONFIG_MACH_SUN4I) || \
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defined(CONFIG_MACH_SUN5I) || \
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defined(CONFIG_MACH_SUN6I) || \
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defined(CONFIG_MACH_SUN7I) || \
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defined(CONFIG_MACH_SUN8I_A23) || \
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defined(CONFIG_MACH_SUN9I)
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#define SUNXI_USB_CSR 0x404
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#else
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#define SUNXI_USB_CSR 0x410
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#endif
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#define SUNXI_USB_PMU_IRQ_ENABLE 0x800
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#define SUNXI_USB_PASSBY_EN 1
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#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
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#define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9)
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#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8)
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#define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0)
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#define REG_PHY_UNK_H3 0x420
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#define REG_PMU_UNK_H3 0x810
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/* A83T specific control bits for PHY0 */
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#define SUNXI_PHY_CTL_VBUSVLDEXT BIT(5)
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#define SUNXI_PHY_CTL_SIDDQ BIT(3)
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/* A83T HSIC specific bits */
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#define SUNXI_EHCI_HS_FORCE BIT(20)
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#define SUNXI_EHCI_CONNECT_DET BIT(17)
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#define SUNXI_EHCI_CONNECT_INT BIT(16)
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#define SUNXI_EHCI_HSIC BIT(1)
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static struct sunxi_usb_phy {
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int usb_rst_mask;
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int gpio_vbus;
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int gpio_vbus_det;
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int gpio_id_det;
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int id;
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int init_count;
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int power_on_count;
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ulong base;
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} sunxi_usb_phy[] = {
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{
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.usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
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.id = 0,
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.base = SUNXI_USB0_BASE,
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},
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{
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.usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
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.id = 1,
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.base = SUNXI_USB1_BASE,
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},
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#if CONFIG_SUNXI_USB_PHYS >= 3
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{
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#ifdef CONFIG_MACH_SUN8I_A83T
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.usb_rst_mask = CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK |
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CCM_USB_CTRL_12M_CLK,
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#else
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.usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
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#endif
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.id = 2,
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.base = SUNXI_USB2_BASE,
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},
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#endif
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#if CONFIG_SUNXI_USB_PHYS >= 4
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{
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.usb_rst_mask = CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK,
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.id = 3,
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.base = SUNXI_USB3_BASE,
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}
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#endif
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};
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static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
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static int get_vbus_gpio(int index)
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{
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switch (index) {
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case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
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case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
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case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
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case 3: return sunxi_name_to_gpio(CONFIG_USB3_VBUS_PIN);
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}
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return -EINVAL;
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}
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static int get_vbus_detect_gpio(int index)
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{
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switch (index) {
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case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET);
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}
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return -EINVAL;
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}
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static int get_id_detect_gpio(int index)
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{
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switch (index) {
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case 0: return sunxi_name_to_gpio(CONFIG_USB0_ID_DET);
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}
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return -EINVAL;
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}
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__maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr,
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int data, int len)
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{
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int j = 0, usbc_bit = 0;
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void *dest = (void *)SUNXI_USB0_BASE + SUNXI_USB_CSR;
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#ifdef CONFIG_MACH_SUN8I_A33
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/* CSR needs to be explicitly initialized to 0 on A33 */
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writel(0, dest);
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#endif
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usbc_bit = 1 << (phy->id * 2);
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for (j = 0; j < len; j++) {
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/* set the bit address to be written */
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clrbits_le32(dest, 0xff << 8);
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setbits_le32(dest, (addr + j) << 8);
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clrbits_le32(dest, usbc_bit);
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/* set data bit */
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if (data & 0x1)
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setbits_le32(dest, 1 << 7);
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else
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clrbits_le32(dest, 1 << 7);
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setbits_le32(dest, usbc_bit);
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clrbits_le32(dest, usbc_bit);
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data >>= 1;
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}
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}
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#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
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static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
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{
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#if defined CONFIG_MACH_SUNXI_H3_H5
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if (phy->id == 0)
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clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
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#endif
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clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02);
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}
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#elif defined CONFIG_MACH_SUN8I_A83T
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static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
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{
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}
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#else
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static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
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{
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/* The following comments are machine
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* translated from Chinese, you have been warned!
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*/
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/* Regulation 45 ohms */
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if (phy->id == 0)
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usb_phy_write(phy, 0x0c, 0x01, 1);
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/* adjust PHY's magnitude and rate */
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usb_phy_write(phy, 0x20, 0x14, 5);
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/* threshold adjustment disconnect */
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#if defined CONFIG_MACH_SUN5I || defined CONFIG_MACH_SUN7I
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usb_phy_write(phy, 0x2a, 2, 2);
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#else
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usb_phy_write(phy, 0x2a, 3, 2);
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#endif
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return;
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}
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#endif
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static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable)
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{
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unsigned long bits = 0;
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void *addr;
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addr = (void *)phy->base + SUNXI_USB_PMU_IRQ_ENABLE;
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bits = SUNXI_EHCI_AHB_ICHR8_EN |
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SUNXI_EHCI_AHB_INCR4_BURST_EN |
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SUNXI_EHCI_AHB_INCRX_ALIGN_EN |
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SUNXI_EHCI_ULPI_BYPASS_EN;
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#ifdef CONFIG_MACH_SUN8I_A83T
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if (phy->id == 2)
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bits |= SUNXI_EHCI_HS_FORCE |
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SUNXI_EHCI_CONNECT_INT |
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SUNXI_EHCI_HSIC;
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#endif
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if (enable)
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setbits_le32(addr, bits);
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else
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clrbits_le32(addr, bits);
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return;
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}
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void sunxi_usb_phy_enable_squelch_detect(int index, int enable)
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{
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#ifndef CONFIG_MACH_SUN8I_A83T
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struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
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usb_phy_write(phy, 0x3c, enable ? 0 : 2, 2);
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#endif
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}
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void sunxi_usb_phy_init(int index)
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{
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struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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phy->init_count++;
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if (phy->init_count != 1)
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return;
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setbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
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sunxi_usb_phy_config(phy);
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if (phy->id != 0)
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sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN);
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#ifdef CONFIG_MACH_SUN8I_A83T
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if (phy->id == 0) {
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setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
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SUNXI_PHY_CTL_VBUSVLDEXT);
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clrbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
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SUNXI_PHY_CTL_SIDDQ);
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}
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#endif
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}
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void sunxi_usb_phy_exit(int index)
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{
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struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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phy->init_count--;
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if (phy->init_count != 0)
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return;
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if (phy->id != 0)
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sunxi_usb_phy_passby(phy, !SUNXI_USB_PASSBY_EN);
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#ifdef CONFIG_MACH_SUN8I_A83T
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if (phy->id == 0) {
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setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
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SUNXI_PHY_CTL_SIDDQ);
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}
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#endif
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clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
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}
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void sunxi_usb_phy_power_on(int index)
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{
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struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
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if (initial_usb_scan_delay) {
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mdelay(initial_usb_scan_delay);
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initial_usb_scan_delay = 0;
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}
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phy->power_on_count++;
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if (phy->power_on_count != 1)
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return;
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if (phy->gpio_vbus >= 0)
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gpio_set_value(phy->gpio_vbus, 1);
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}
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void sunxi_usb_phy_power_off(int index)
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{
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struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
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phy->power_on_count--;
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if (phy->power_on_count != 0)
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return;
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if (phy->gpio_vbus >= 0)
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gpio_set_value(phy->gpio_vbus, 0);
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}
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int sunxi_usb_phy_vbus_detect(int index)
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{
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struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
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int err, retries = 3;
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if (phy->gpio_vbus_det < 0)
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return phy->gpio_vbus_det;
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err = gpio_get_value(phy->gpio_vbus_det);
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/*
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* Vbus may have been provided by the board and just been turned of
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* some milliseconds ago on reset, what we're measuring then is a
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* residual charge on Vbus, sleep a bit and try again.
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*/
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while (err > 0 && retries--) {
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mdelay(100);
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err = gpio_get_value(phy->gpio_vbus_det);
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}
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return err;
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}
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int sunxi_usb_phy_id_detect(int index)
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{
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struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
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if (phy->gpio_id_det < 0)
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return phy->gpio_id_det;
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return gpio_get_value(phy->gpio_id_det);
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}
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int sunxi_usb_phy_probe(void)
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{
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct sunxi_usb_phy *phy;
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int i, ret = 0;
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for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
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phy = &sunxi_usb_phy[i];
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phy->gpio_vbus = get_vbus_gpio(i);
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if (phy->gpio_vbus >= 0) {
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ret = gpio_request(phy->gpio_vbus, "usb_vbus");
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if (ret)
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return ret;
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ret = gpio_direction_output(phy->gpio_vbus, 0);
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if (ret)
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return ret;
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}
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phy->gpio_vbus_det = get_vbus_detect_gpio(i);
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if (phy->gpio_vbus_det >= 0) {
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ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
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if (ret)
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return ret;
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ret = gpio_direction_input(phy->gpio_vbus_det);
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if (ret)
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return ret;
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}
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phy->gpio_id_det = get_id_detect_gpio(i);
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if (phy->gpio_id_det >= 0) {
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ret = gpio_request(phy->gpio_id_det, "usb_id_det");
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if (ret)
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return ret;
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ret = gpio_direction_input(phy->gpio_id_det);
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if (ret)
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return ret;
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sunxi_gpio_set_pull(phy->gpio_id_det,
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SUNXI_GPIO_PULL_UP);
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}
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}
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setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
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return 0;
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}
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int sunxi_usb_phy_remove(void)
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{
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct sunxi_usb_phy *phy;
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int i;
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clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
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for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
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phy = &sunxi_usb_phy[i];
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if (phy->gpio_vbus >= 0)
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gpio_free(phy->gpio_vbus);
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if (phy->gpio_vbus_det >= 0)
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gpio_free(phy->gpio_vbus_det);
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if (phy->gpio_id_det >= 0)
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gpio_free(phy->gpio_id_det);
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}
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return 0;
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}
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