mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-23 10:28:51 +09:00
![Tom Rini](/assets/img/avatar_default.png)
This moves what was in arch/arm/cpu/armv7/omap-common in to arch/arm/mach-omap2 and moves arch/arm/cpu/armv7/{am33xx,omap3,omap4,omap5} in to arch/arm/mach-omap2 as subdirectories. All refernces to the former locations are updated to the current locations. For the logic to decide what our outputs are, consolidate the tests into a single config.mk rather than including 4. Signed-off-by: Tom Rini <trini@konsulko.com>
232 lines
5.8 KiB
C
232 lines
5.8 KiB
C
/*
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* TI PIPE3 PHY
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*
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* (C) Copyright 2013
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* Texas Instruments, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <sata.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include "pipe3-phy.h"
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/* PLLCTRL Registers */
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#define PLL_STATUS 0x00000004
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#define PLL_GO 0x00000008
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#define PLL_CONFIGURATION1 0x0000000C
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#define PLL_CONFIGURATION2 0x00000010
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#define PLL_CONFIGURATION3 0x00000014
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#define PLL_CONFIGURATION4 0x00000020
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#define PLL_REGM_MASK 0x001FFE00
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#define PLL_REGM_SHIFT 9
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#define PLL_REGM_F_MASK 0x0003FFFF
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#define PLL_REGM_F_SHIFT 0
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#define PLL_REGN_MASK 0x000001FE
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#define PLL_REGN_SHIFT 1
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#define PLL_SELFREQDCO_MASK 0x0000000E
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#define PLL_SELFREQDCO_SHIFT 1
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#define PLL_SD_MASK 0x0003FC00
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#define PLL_SD_SHIFT 10
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#define SET_PLL_GO 0x1
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#define PLL_TICOPWDN BIT(16)
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#define PLL_LDOPWDN BIT(15)
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#define PLL_LOCK 0x2
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#define PLL_IDLE 0x1
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/* PHY POWER CONTROL Register */
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
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#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
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#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
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#define PLL_IDLE_TIME 100 /* in milliseconds */
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#define PLL_LOCK_TIME 100 /* in milliseconds */
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static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
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{
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return __raw_readl(addr + offset);
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}
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static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
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u32 data)
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{
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__raw_writel(data, addr + offset);
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}
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static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
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*pipe3)
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{
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u32 rate;
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struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
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rate = get_sys_clk_freq();
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for (; dpll_map->rate; dpll_map++) {
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if (rate == dpll_map->rate)
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return &dpll_map->params;
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}
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printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
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__func__, rate);
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return NULL;
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}
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static int omap_pipe3_wait_lock(struct omap_pipe3 *phy)
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{
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u32 val;
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int timeout = PLL_LOCK_TIME;
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do {
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mdelay(1);
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val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
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if (val & PLL_LOCK)
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break;
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} while (--timeout);
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if (!(val & PLL_LOCK)) {
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printf("%s: DPLL failed to lock\n", __func__);
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return -EBUSY;
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}
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return 0;
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}
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static int omap_pipe3_dpll_program(struct omap_pipe3 *phy)
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{
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u32 val;
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struct pipe3_dpll_params *dpll_params;
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dpll_params = omap_pipe3_get_dpll_params(phy);
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if (!dpll_params) {
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printf("%s: Invalid DPLL parameters\n", __func__);
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return -EINVAL;
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}
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val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
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val &= ~PLL_REGN_MASK;
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val |= dpll_params->n << PLL_REGN_SHIFT;
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omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
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val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
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val &= ~PLL_SELFREQDCO_MASK;
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val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
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omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
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val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
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val &= ~PLL_REGM_MASK;
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val |= dpll_params->m << PLL_REGM_SHIFT;
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omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
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val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
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val &= ~PLL_REGM_F_MASK;
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val |= dpll_params->mf << PLL_REGM_F_SHIFT;
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omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
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val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
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val &= ~PLL_SD_MASK;
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val |= dpll_params->sd << PLL_SD_SHIFT;
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omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
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omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
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return omap_pipe3_wait_lock(phy);
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}
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static void omap_control_phy_power(struct omap_pipe3 *phy, int on)
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{
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u32 val, rate;
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val = readl(phy->power_reg);
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rate = get_sys_clk_freq();
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rate = rate/1000000;
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if (on) {
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val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
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OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
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val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
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OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
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val |= rate <<
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OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
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} else {
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val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
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val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
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OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
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}
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writel(val, phy->power_reg);
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}
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int phy_pipe3_power_on(struct omap_pipe3 *phy)
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{
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int ret;
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u32 val;
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/* Program the DPLL only if not locked */
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val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
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if (!(val & PLL_LOCK)) {
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ret = omap_pipe3_dpll_program(phy);
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if (ret)
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return ret;
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} else {
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/* else just bring it out of IDLE mode */
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val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
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if (val & PLL_IDLE) {
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val &= ~PLL_IDLE;
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omap_pipe3_writel(phy->pll_ctrl_base,
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PLL_CONFIGURATION2, val);
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ret = omap_pipe3_wait_lock(phy);
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if (ret)
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return ret;
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}
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}
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/* Power up the PHY */
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omap_control_phy_power(phy, 1);
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return 0;
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}
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int phy_pipe3_power_off(struct omap_pipe3 *phy)
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{
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u32 val;
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int timeout = PLL_IDLE_TIME;
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/* Power down the PHY */
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omap_control_phy_power(phy, 0);
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/* Put DPLL in IDLE mode */
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val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
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val |= PLL_IDLE;
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omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
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/* wait for LDO and Oscillator to power down */
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do {
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mdelay(1);
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val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
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if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
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break;
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} while (--timeout);
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if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
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printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
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__func__, val);
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return -EBUSY;
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}
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return 0;
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}
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