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![Simon Glass](/assets/img/avatar_default.png)
This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detected. Unfortunately this involves changing a lot of places in the code. I have not changed behvaiour to return an error where one is not currently returned, to avoid unexpected breakage. Eventually it would be nice to allow boards to register functions to be called to update the device tree. This would avoid all the many functions to do this. However it's not clear yet if this should be done using driver model or with a linker list. This work is left for later. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
227 lines
5.3 KiB
C
227 lines
5.3 KiB
C
/*
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* sbc8349.c -- WindRiver SBC8349 board support.
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* Copyright (c) 2006-2007 Wind River Systems, Inc.
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*
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* Paul Gortmaker <paul.gortmaker@windriver.com>
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* Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <asm/mpc8349_pci.h>
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#include <i2c.h>
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#include <spd_sdram.h>
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#include <miiphy.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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int fixed_sdram(void);
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void sdram_init(void);
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#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
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void ddr_enable_ecc(unsigned int dram_size);
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#endif
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f (void)
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{
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return 0;
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}
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#endif
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#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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return -1;
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/* DDR SDRAM - Main SODIMM */
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
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#if defined(CONFIG_SPD_EEPROM)
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msize = spd_sdram();
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#else
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msize = fixed_sdram();
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#endif
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/*
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* Initialize SDRAM if it is on local bus.
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*/
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sdram_init();
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize and enable DDR ECC.
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*/
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ddr_enable_ecc(msize * 1024 * 1024);
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#endif
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/* return total bus SDRAM size(bytes) -- DDR */
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return (msize * 1024 * 1024);
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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int fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = CONFIG_SYS_DDR_SIZE;
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u32 ddr_size = msize << 20; /* DDR size in bytes */
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u32 ddr_size_log2 = __ilog2(msize);
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
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#if (CONFIG_SYS_DDR_SIZE != 256)
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#warning Currently any ddr size other than 256 is not supported
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#endif
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#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
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#warning Chip select bounds is only configurable in 16MB increments
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#endif
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im->ddr.csbnds[2].csbnds =
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((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
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(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
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CSBNDS_EA_SHIFT) & CSBNDS_EA);
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im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
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/* currently we use only one CS, so disable the other banks */
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im->ddr.cs_config[0] = 0;
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im->ddr.cs_config[1] = 0;
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im->ddr.cs_config[3] = 0;
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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im->ddr.sdram_cfg =
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SDRAM_CFG_SREN
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#if defined(CONFIG_DDR_2T_TIMING)
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| SDRAM_CFG_2T_EN
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#endif
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| SDRAM_CFG_SDRAM_TYPE_DDR1;
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#if defined (CONFIG_DDR_32BIT)
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/* for 32-bit mode burst length is 8 */
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im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
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#endif
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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udelay(200);
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/* enable DDR controller */
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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return msize;
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}
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#endif/*!CONFIG_SYS_SPD_EEPROM*/
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int checkboard (void)
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{
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puts("Board: Wind River SBC834x\n");
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return 0;
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}
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/*
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* if board is fitted with SDRAM
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*/
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#if defined(CONFIG_SYS_BR2_PRELIM) \
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&& defined(CONFIG_SYS_OR2_PRELIM) \
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&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
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&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
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/*
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* Initialize SDRAM memory on the Local Bus.
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*/
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void sdram_init(void)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile fsl_lbc_t *lbc = &immap->im_lbc;
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uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
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puts("\n SDRAM on Local Bus: ");
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print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
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/*
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* Setup SDRAM Base and Option Registers, already done in cpu_init.c
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*/
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/* setup mtrpt, lsrt and lbcr for LB bus */
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lbc->lbcr = CONFIG_SYS_LBC_LBCR;
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lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
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lbc->lsrt = CONFIG_SYS_LBC_LSRT;
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asm("sync");
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/*
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* Configure the SDRAM controller Machine Mode Register.
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*/
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
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asm("sync");
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/*1 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*2 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*3 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*4 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*5 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*6 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*7 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*8 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/* 0x58636733; mode register write operation */
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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}
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#else
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void sdram_init(void)
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{
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puts(" SDRAM on Local Bus: Disabled in config\n");
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}
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#endif
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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return 0;
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}
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#endif
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