mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-19 19:23:21 +09:00
b2d5ac5985
This adds NAND boot support for LS2085AQDS, using SPL framework.
Details of forming NAND image can be found in README.
Signed-off-by: Scott Wood <scottwood@freescale.com>
[York Sun: Remove +S from defconfig after commit 252ed872]
Signed-off-by: York Sun <yorksun@freescale.com>
74 lines
1.4 KiB
C
74 lines
1.4 KiB
C
/*
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* Copyright 2015 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fsl_ifc.h>
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#include <nand.h>
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#include <spl.h>
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#include <asm/arch-fsl-lsch3/soc.h>
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#include <asm/io.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void erratum_a008751(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008751
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u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
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writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4);
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#endif
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}
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static void erratum_rcw_src(void)
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{
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#if defined(CONFIG_SPL)
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u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
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u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
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u32 val;
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val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
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val &= ~DCFG_PORSR1_RCW_SRC;
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val |= DCFG_PORSR1_RCW_SRC_NOR;
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out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
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#endif
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}
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void fsl_lsch3_early_init_f(void)
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{
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erratum_a008751();
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erratum_rcw_src();
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init_early_memctl_regs(); /* tighten IFC timing */
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}
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#ifdef CONFIG_SPL_BUILD
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void board_init_f(ulong dummy)
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{
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/* Clear global data */
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memset((void *)gd, 0, sizeof(gd_t));
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arch_cpu_init();
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board_early_init_f();
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timer_init();
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env_init();
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gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
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serial_init();
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console_init_f();
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dram_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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board_init_r(NULL, 0);
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}
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_NAND;
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}
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#endif
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