mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-04 02:20:43 +09:00
b2c860c6dc
The RISC-V arch incorrectly uses 32-bit instead of 64-bit variables in several places. Fix this. In addition, BITS_PER_LONG is set to 64 on RV64I systems. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
76 lines
1.5 KiB
C
76 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2016-17 Microsemi Corporation.
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* Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
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*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*/
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#include <common.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/encoding.h>
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static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs);
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int interrupt_init(void)
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{
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return 0;
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}
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/*
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* enable interrupts
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*/
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void enable_interrupts(void)
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{
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}
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/*
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* disable interrupts
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*/
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int disable_interrupts(void)
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{
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return 0;
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}
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ulong handle_trap(ulong mcause, ulong epc, struct pt_regs *regs)
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{
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ulong is_int;
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is_int = (mcause & MCAUSE_INT);
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if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT))
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external_interrupt(0); /* handle_m_ext_interrupt */
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else if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER))
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timer_interrupt(0); /* handle_m_timer_interrupt */
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else
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_exit_trap(mcause, epc, regs);
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return epc;
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}
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/*
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*Entry Point for PLIC Interrupt Handler
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*/
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__attribute__((weak)) void external_interrupt(struct pt_regs *regs)
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{
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}
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__attribute__((weak)) void timer_interrupt(struct pt_regs *regs)
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{
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}
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static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
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{
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static const char * const exception_code[] = {
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"Instruction address misaligned",
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"Instruction access fault",
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"Illegal instruction",
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"Breakpoint",
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"Load address misaligned"
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};
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printf("exception code: %ld , %s , epc %lx , ra %lx\n",
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code, exception_code[code], epc, regs->ra);
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}
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