mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
1cf6825a68
There is no need to keep a separate coreboot_fb.dtsi since now we have a generic coreboot payload dts. While we are here, this also remove the out-of-date description in the documentation regarding to coreboot framebuffer driver with U-Boot loaded as a payload from coreboot. As the testing result with QEMU 2.5.0 shows, the driver just works like a charm. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
88 lines
1.5 KiB
Plaintext
88 lines
1.5 KiB
Plaintext
/dts-v1/;
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/include/ "skeleton.dtsi"
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/include/ "serial.dtsi"
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/include/ "reset.dtsi"
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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/ {
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model = "Google Panther";
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compatible = "google,panther", "intel,haswell";
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aliases {
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spi0 = &spi;
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};
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config {
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silent-console = <0>;
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no-keyboard;
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};
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chosen {
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stdout-path = "/serial";
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};
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pci {
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compatible = "pci-x86";
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#address-cells = <3>;
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#size-cells = <2>;
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u-boot,dm-pre-reloc;
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ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
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0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
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0x01000000 0x0 0x1000 0x1000 0 0xf000>;
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pch@1f,0 {
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reg = <0x0000f800 0 0 0 0>;
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compatible = "intel,pch9";
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#address-cells = <1>;
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#size-cells = <1>;
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spi: spi {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ich9-spi";
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spi-flash@0 {
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#size-cells = <1>;
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#address-cells = <1>;
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reg = <0>;
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compatible = "winbond,w25q64",
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"spi-flash";
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memory-map = <0xff800000 0x00800000>;
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rw-mrc-cache {
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label = "rw-mrc-cache";
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reg = <0x003e0000 0x00010000>;
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};
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};
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};
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gpioa {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0 0x10>;
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bank-name = "A";
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};
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gpiob {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x30 0x10>;
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bank-name = "B";
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};
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gpioc {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x40 0x10>;
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bank-name = "C";
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};
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};
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};
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tpm {
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reg = <0xfed40000 0x5000>;
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compatible = "infineon,slb9635lpc";
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};
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};
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