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https://github.com/brain-hackers/u-boot-brain
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58dac32764
Before this commit, CONFIG_MPC8260 and CONFIG_8260
were used mixed-up.
All boards with mpc8260 cpu defined both of them:
- CONFIG_MPC8260 was defined in board config headers
and include/common.h
- CONFIG_8260 was defined arch/powerpc/cpu/mpc8260/config.mk
We do not need to have both of them.
This commit keeps only CONFIG_MPC8260.
This commit does:
- Delete CONFIG_8260 and CONFIG_MPC8260 definition
in config headers and include/common.h
- Rename CONFIG_8260 to CONFIG_MPC8260
in arch/powerpc/cpu/mpc8260/config.mk.
- Rename #ifdef CONFIG_8260 to #ifdef CONFIG_MPC8260
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
54 lines
911 B
ArmAsm
54 lines
911 B
ArmAsm
/*
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* Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <command.h>
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#include <mpc8260.h>
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#include <version.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#if defined(CONFIG_CMD_KGDB)
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/*
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* cache flushing routines for kgdb
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*/
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.globl kgdb_flush_cache_all
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kgdb_flush_cache_all:
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mfspr r3, HID0
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ori r3, r3, HID0_ICFI|HID0_DCI /* Invalidate All */
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SYNC
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mtspr HID0, r3
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blr
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.globl kgdb_flush_cache_range
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kgdb_flush_cache_range:
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li r5,CONFIG_SYS_CACHELINE_SIZE-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT
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beqlr
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mtctr r4
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mr r6,r3
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1: dcbst 0,r3
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addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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mtctr r4
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2: icbi 0,r6
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addi r6,r6,CONFIG_SYS_CACHELINE_SIZE
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bdnz 2b
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SYNC
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blr
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#endif
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