mirror of
https://github.com/brain-hackers/u-boot-brain
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410 lines
11 KiB
C
410 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* Adapted from coreboot src/arch/x86/boot/mpspec.c
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <log.h>
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#include <asm/cpu.h>
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#include <asm/irq.h>
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#include <asm/ioapic.h>
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#include <asm/lapic.h>
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#include <asm/mpspec.h>
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#include <asm/tables.h>
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#include <dm/uclass-internal.h>
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DECLARE_GLOBAL_DATA_PTR;
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static bool isa_irq_occupied[16];
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struct mp_config_table *mp_write_floating_table(struct mp_floating_table *mf)
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{
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ulong mc;
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memcpy(mf->mpf_signature, MPF_SIGNATURE, 4);
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mf->mpf_physptr = (ulong)mf + sizeof(struct mp_floating_table);
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mf->mpf_length = 1;
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mf->mpf_spec = MPSPEC_V14;
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mf->mpf_checksum = 0;
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/* We don't use the default configuration table */
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mf->mpf_feature1 = 0;
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/* Indicate that virtual wire mode is always implemented */
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mf->mpf_feature2 = 0;
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mf->mpf_feature3 = 0;
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mf->mpf_feature4 = 0;
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mf->mpf_feature5 = 0;
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mf->mpf_checksum = table_compute_checksum(mf, mf->mpf_length * 16);
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mc = (ulong)mf + sizeof(struct mp_floating_table);
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return (struct mp_config_table *)mc;
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}
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void mp_config_table_init(struct mp_config_table *mc)
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{
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memcpy(mc->mpc_signature, MPC_SIGNATURE, 4);
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mc->mpc_length = sizeof(struct mp_config_table);
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mc->mpc_spec = MPSPEC_V14;
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mc->mpc_checksum = 0;
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mc->mpc_oemptr = 0;
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mc->mpc_oemsize = 0;
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mc->mpc_entry_count = 0;
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mc->mpc_lapic = LAPIC_DEFAULT_BASE;
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mc->mpe_length = 0;
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mc->mpe_checksum = 0;
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mc->reserved = 0;
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/* The oem/product id fields are exactly 8/12 bytes long */
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table_fill_string(mc->mpc_oem, CONFIG_SYS_VENDOR, 8, ' ');
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table_fill_string(mc->mpc_product, CONFIG_SYS_BOARD, 12, ' ');
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}
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void mp_write_processor(struct mp_config_table *mc)
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{
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struct mpc_config_processor *mpc;
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struct udevice *dev;
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u8 boot_apicid, apicver;
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u32 cpusignature, cpufeature;
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struct cpuid_result result;
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boot_apicid = lapicid();
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apicver = lapic_read(LAPIC_LVR) & 0xff;
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result = cpuid(1);
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cpusignature = result.eax;
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cpufeature = result.edx;
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for (uclass_find_first_device(UCLASS_CPU, &dev);
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dev;
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uclass_find_next_device(&dev)) {
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struct cpu_platdata *plat = dev_get_parent_platdata(dev);
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u8 cpuflag = MPC_CPU_EN;
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if (!device_active(dev))
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continue;
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mpc = (struct mpc_config_processor *)mp_next_mpc_entry(mc);
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mpc->mpc_type = MP_PROCESSOR;
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mpc->mpc_apicid = plat->cpu_id;
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mpc->mpc_apicver = apicver;
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if (boot_apicid == plat->cpu_id)
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cpuflag |= MPC_CPU_BP;
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mpc->mpc_cpuflag = cpuflag;
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mpc->mpc_cpusignature = cpusignature;
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mpc->mpc_cpufeature = cpufeature;
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mpc->mpc_reserved[0] = 0;
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mpc->mpc_reserved[1] = 0;
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mp_add_mpc_entry(mc, sizeof(*mpc));
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}
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}
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void mp_write_bus(struct mp_config_table *mc, int id, const char *bustype)
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{
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struct mpc_config_bus *mpc;
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mpc = (struct mpc_config_bus *)mp_next_mpc_entry(mc);
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mpc->mpc_type = MP_BUS;
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mpc->mpc_busid = id;
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memcpy(mpc->mpc_bustype, bustype, 6);
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mp_add_mpc_entry(mc, sizeof(*mpc));
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}
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void mp_write_ioapic(struct mp_config_table *mc, int id, int ver, u32 apicaddr)
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{
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struct mpc_config_ioapic *mpc;
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mpc = (struct mpc_config_ioapic *)mp_next_mpc_entry(mc);
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mpc->mpc_type = MP_IOAPIC;
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mpc->mpc_apicid = id;
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mpc->mpc_apicver = ver;
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mpc->mpc_flags = MPC_APIC_USABLE;
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mpc->mpc_apicaddr = apicaddr;
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mp_add_mpc_entry(mc, sizeof(*mpc));
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}
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void mp_write_intsrc(struct mp_config_table *mc, int irqtype, int irqflag,
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int srcbus, int srcbusirq, int dstapic, int dstirq)
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{
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struct mpc_config_intsrc *mpc;
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mpc = (struct mpc_config_intsrc *)mp_next_mpc_entry(mc);
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mpc->mpc_type = MP_INTSRC;
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mpc->mpc_irqtype = irqtype;
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mpc->mpc_irqflag = irqflag;
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mpc->mpc_srcbus = srcbus;
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mpc->mpc_srcbusirq = srcbusirq;
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mpc->mpc_dstapic = dstapic;
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mpc->mpc_dstirq = dstirq;
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mp_add_mpc_entry(mc, sizeof(*mpc));
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}
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void mp_write_pci_intsrc(struct mp_config_table *mc, int irqtype,
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int srcbus, int dev, int pin, int dstapic, int dstirq)
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{
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u8 srcbusirq = (dev << 2) | (pin - 1);
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mp_write_intsrc(mc, irqtype, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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srcbus, srcbusirq, dstapic, dstirq);
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}
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void mp_write_lintsrc(struct mp_config_table *mc, int irqtype, int irqflag,
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int srcbus, int srcbusirq, int destapic, int destlint)
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{
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struct mpc_config_lintsrc *mpc;
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mpc = (struct mpc_config_lintsrc *)mp_next_mpc_entry(mc);
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mpc->mpc_type = MP_LINTSRC;
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mpc->mpc_irqtype = irqtype;
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mpc->mpc_irqflag = irqflag;
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mpc->mpc_srcbusid = srcbus;
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mpc->mpc_srcbusirq = srcbusirq;
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mpc->mpc_destapic = destapic;
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mpc->mpc_destlint = destlint;
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mp_add_mpc_entry(mc, sizeof(*mpc));
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}
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void mp_write_address_space(struct mp_config_table *mc,
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int busid, int addr_type,
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u32 addr_base_low, u32 addr_base_high,
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u32 addr_length_low, u32 addr_length_high)
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{
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struct mp_ext_system_address_space *mpe;
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mpe = (struct mp_ext_system_address_space *)mp_next_mpe_entry(mc);
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mpe->mpe_type = MPE_SYSTEM_ADDRESS_SPACE;
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mpe->mpe_length = sizeof(*mpe);
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mpe->mpe_busid = busid;
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mpe->mpe_addr_type = addr_type;
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mpe->mpe_addr_base_low = addr_base_low;
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mpe->mpe_addr_base_high = addr_base_high;
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mpe->mpe_addr_length_low = addr_length_low;
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mpe->mpe_addr_length_high = addr_length_high;
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mp_add_mpe_entry(mc, (struct mp_ext_config *)mpe);
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}
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void mp_write_bus_hierarchy(struct mp_config_table *mc,
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int busid, int bus_info, int parent_busid)
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{
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struct mp_ext_bus_hierarchy *mpe;
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mpe = (struct mp_ext_bus_hierarchy *)mp_next_mpe_entry(mc);
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mpe->mpe_type = MPE_BUS_HIERARCHY;
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mpe->mpe_length = sizeof(*mpe);
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mpe->mpe_busid = busid;
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mpe->mpe_bus_info = bus_info;
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mpe->mpe_parent_busid = parent_busid;
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mpe->reserved[0] = 0;
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mpe->reserved[1] = 0;
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mpe->reserved[2] = 0;
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mp_add_mpe_entry(mc, (struct mp_ext_config *)mpe);
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}
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void mp_write_compat_address_space(struct mp_config_table *mc, int busid,
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int addr_modifier, u32 range_list)
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{
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struct mp_ext_compat_address_space *mpe;
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mpe = (struct mp_ext_compat_address_space *)mp_next_mpe_entry(mc);
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mpe->mpe_type = MPE_COMPAT_ADDRESS_SPACE;
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mpe->mpe_length = sizeof(*mpe);
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mpe->mpe_busid = busid;
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mpe->mpe_addr_modifier = addr_modifier;
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mpe->mpe_range_list = range_list;
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mp_add_mpe_entry(mc, (struct mp_ext_config *)mpe);
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}
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u32 mptable_finalize(struct mp_config_table *mc)
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{
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ulong end;
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mc->mpe_checksum = table_compute_checksum((void *)mp_next_mpc_entry(mc),
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mc->mpe_length);
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mc->mpc_checksum = table_compute_checksum(mc, mc->mpc_length);
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end = mp_next_mpe_entry(mc);
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debug("Write the MP table at: %lx - %lx\n", (ulong)mc, end);
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return end;
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}
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static void mptable_add_isa_interrupts(struct mp_config_table *mc, int bus_isa,
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int apicid, int external_int2)
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{
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int i;
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mp_write_intsrc(mc, external_int2 ? MP_INT : MP_EXTINT,
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MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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bus_isa, 0, apicid, 0);
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mp_write_intsrc(mc, MP_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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bus_isa, 1, apicid, 1);
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mp_write_intsrc(mc, external_int2 ? MP_EXTINT : MP_INT,
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MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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bus_isa, 0, apicid, 2);
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for (i = 3; i < 16; i++) {
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/*
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* Do not write ISA interrupt entry if it is already occupied
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* by the platform devices.
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*/
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if (isa_irq_occupied[i])
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continue;
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mp_write_intsrc(mc, MP_INT,
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MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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bus_isa, i, apicid, i);
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}
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}
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/*
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* Check duplicated I/O interrupt assignment table entry, to make sure
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* there is only one entry with the given bus, device and interrupt pin.
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*/
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static bool check_dup_entry(struct mpc_config_intsrc *intsrc_base,
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int entry_num, int bus, int device, int pin)
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{
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struct mpc_config_intsrc *intsrc = intsrc_base;
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int i;
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for (i = 0; i < entry_num; i++) {
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if (intsrc->mpc_srcbus == bus &&
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intsrc->mpc_srcbusirq == ((device << 2) | (pin - 1)))
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break;
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intsrc++;
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}
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return (i == entry_num) ? false : true;
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}
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/* TODO: move this to driver model */
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__weak int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
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{
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/* PIRQ[A-H] are connected to I/O APIC INTPIN#16-23 */
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return pirq + 16;
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}
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static int mptable_add_intsrc(struct mp_config_table *mc,
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int bus_isa, int apicid)
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{
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struct mpc_config_intsrc *intsrc_base;
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int intsrc_entries = 0;
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const void *blob = gd->fdt_blob;
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struct udevice *dev;
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int len, count;
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const u32 *cell;
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int i, ret;
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ret = uclass_first_device_err(UCLASS_IRQ, &dev);
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if (ret && ret != -ENODEV) {
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debug("%s: Cannot find irq router node\n", __func__);
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return ret;
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}
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/* Get I/O interrupt information from device tree */
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cell = fdt_getprop(blob, dev_of_offset(dev), "intel,pirq-routing",
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&len);
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if (!cell)
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return -ENOENT;
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if ((len % sizeof(struct pirq_routing)) == 0)
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count = len / sizeof(struct pirq_routing);
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else
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return -EINVAL;
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intsrc_base = (struct mpc_config_intsrc *)mp_next_mpc_entry(mc);
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for (i = 0; i < count; i++) {
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struct pirq_routing pr;
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int bus, dev, func;
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int dstirq;
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pr.bdf = fdt_addr_to_cpu(cell[0]);
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pr.pin = fdt_addr_to_cpu(cell[1]);
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pr.pirq = fdt_addr_to_cpu(cell[2]);
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bus = PCI_BUS(pr.bdf);
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dev = PCI_DEV(pr.bdf);
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func = PCI_FUNC(pr.bdf);
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if (check_dup_entry(intsrc_base, intsrc_entries,
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bus, dev, pr.pin)) {
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debug("found entry for bus %d device %d INT%c, skipping\n",
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bus, dev, 'A' + pr.pin - 1);
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cell += sizeof(struct pirq_routing) / sizeof(u32);
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continue;
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}
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dstirq = mp_determine_pci_dstirq(bus, dev, func, pr.pirq);
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/*
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* For PIRQ which is connected to I/O APIC interrupt pin#0-15,
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* mark it as occupied so that we can skip it later.
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*/
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if (dstirq < 16)
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isa_irq_occupied[dstirq] = true;
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mp_write_pci_intsrc(mc, MP_INT, bus, dev, pr.pin,
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apicid, dstirq);
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intsrc_entries++;
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cell += sizeof(struct pirq_routing) / sizeof(u32);
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}
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/* Legacy Interrupts */
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debug("Writing ISA IRQs\n");
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mptable_add_isa_interrupts(mc, bus_isa, apicid, 0);
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return 0;
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}
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static void mptable_add_lintsrc(struct mp_config_table *mc, int bus_isa)
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{
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mp_write_lintsrc(mc, MP_EXTINT,
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MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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bus_isa, 0, MP_APIC_ALL, 0);
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mp_write_lintsrc(mc, MP_NMI,
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MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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bus_isa, 0, MP_APIC_ALL, 1);
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}
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ulong write_mp_table(ulong addr)
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{
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struct mp_config_table *mc;
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int ioapic_id, ioapic_ver;
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int bus_isa = 0xff;
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int ret;
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ulong end;
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/* 16 byte align the table address */
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addr = ALIGN(addr, 16);
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/* Write floating table */
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mc = mp_write_floating_table((struct mp_floating_table *)addr);
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/* Write configuration table header */
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mp_config_table_init(mc);
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/* Write processor entry */
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mp_write_processor(mc);
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/* Write bus entry */
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mp_write_bus(mc, bus_isa, BUSTYPE_ISA);
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/* Write I/O APIC entry */
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ioapic_id = io_apic_read(IO_APIC_ID) >> 24;
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ioapic_ver = io_apic_read(IO_APIC_VER) & 0xff;
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mp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
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/* Write I/O interrupt assignment entry */
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ret = mptable_add_intsrc(mc, bus_isa, ioapic_id);
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if (ret)
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debug("Failed to write I/O interrupt assignment table\n");
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/* Write local interrupt assignment entry */
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mptable_add_lintsrc(mc, bus_isa);
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/* Finalize the MP table */
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end = mptable_finalize(mc);
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return end;
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}
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