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https://github.com/brain-hackers/u-boot-brain
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d9434a17e5
Add common x86 ASL files, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
142 lines
3.3 KiB
Plaintext
142 lines
3.3 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*/
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/* Intel LPC/eSPI Bus Device - 0:1f.0 */
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#include <asm/arch/iomap.h>
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Device (LPCB)
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{
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Name (_ADR, 0x001f0000)
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Name (_DDN, "LPC Bus Device")
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/* DMA Controller */
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Device (DMAC)
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{
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Name (_HID, EISAID("PNP0200"))
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Name (_CRS, ResourceTemplate()
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{
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IO (Decode16, 0x00, 0x00, 0x01, 0x20)
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IO (Decode16, 0x81, 0x81, 0x01, 0x11)
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IO (Decode16, 0x93, 0x93, 0x01, 0x0d)
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IO (Decode16, 0xc0, 0xc0, 0x01, 0x20)
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DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 }
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})
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}
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/* Firmware Hub */
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Device (FWH)
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{
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Name (_HID, EISAID ("INT0800"))
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Name (_DDN, "Firmware Hub")
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Name (_CRS, ResourceTemplate ()
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{
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Memory32Fixed (ReadOnly, 0xff000000, 0x01000000)
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})
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}
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/* High Precision Event Timer */
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Device (HPET)
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{
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Name (_HID, EISAID ("PNP0103"))
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Name (_CID, 0x010CD041)
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Name (_DDN, "High Precision Event Timer")
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Name (_CRS, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
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})
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Method (_STA, 0)
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{
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Return (0xF)
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}
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}
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/* FPU */
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Device(MATH)
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{
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Name (_HID, EISAID("PNP0C04"))
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Name (_CRS, ResourceTemplate()
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{
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IO (Decode16, 0xf0, 0xf0, 0x01, 0x01)
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IRQNoFlags() { 13 }
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})
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}
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/* AT Interrupt Controller */
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Device (PIC)
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{
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Name (_HID, EISAID ("PNP0000"))
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Name (_DDN, "8259 Interrupt Controller")
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Name (_CRS, ResourceTemplate()
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{
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IO (Decode16, 0x20, 0x20, 0x01, 0x02)
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IO (Decode16, 0x24, 0x24, 0x01, 0x02)
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IO (Decode16, 0x28, 0x28, 0x01, 0x02)
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IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
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IO (Decode16, 0x30, 0x30, 0x01, 0x02)
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IO (Decode16, 0x34, 0x34, 0x01, 0x02)
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IO (Decode16, 0x38, 0x38, 0x01, 0x02)
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IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
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IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
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IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
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IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
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IO (Decode16, 0xac, 0xac, 0x01, 0x02)
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IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
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IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
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IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
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IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
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IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
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IRQNoFlags () { 2 }
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})
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}
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/* LPC device: Resource consumption */
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Device (LDRC)
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{
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Name (_HID, EISAID ("PNP0C02"))
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Name (_UID, 2)
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Name (_DDN, "Legacy Device Resources")
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
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IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
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IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
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IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
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IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
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IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
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IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
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IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
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IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
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IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,
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0x1, 0xff)
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})
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}
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/* Real Time Clock Device */
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Device (RTC)
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{
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Name (_HID, EISAID ("PNP0B00"))
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Name (_DDN, "Real Time Clock")
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, 0x70, 0x70, 1, 8)
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})
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}
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/* Timer */
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Device (TIMR)
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{
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Name (_HID, EISAID ("PNP0100"))
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Name (_DDN, "8254 Timer")
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, 0x40, 0x40, 0x01, 0x04)
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IO (Decode16, 0x50, 0x50, 0x10, 0x04)
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IRQNoFlags () {0}
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})
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}
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}
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