mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-16 17:53:38 +09:00
d1eee7eed9
iMX8MP has 6 fused parts in each qualification tier, with core, VPU, ISP, NPU or DSP fused respectively. The configuration tables for enabled modules: MIMX8ML8DVNLZAA Quad Core, VPU, NPU, ISP, DSP MIMX8ML7DVNLZAA Quad Core, NPU, ISP MIMX8ML6DVNLZAA Quad Core, VPU, ISP MIMX8ML5DVNLZAA Quad Core, VPU MIMX8ML4DVNLZAA Quad Lite MIMX8ML3DVNLZAA Dual Core, VPU, NPU, ISP, DSP Add the support in U-Boot Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
91 lines
2.8 KiB
C
91 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2014 Freescale Semiconductor, Inc.
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*/
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#define MXC_CPU_MX23 0x23
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#define MXC_CPU_MX25 0x25
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#define MXC_CPU_MX27 0x27
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#define MXC_CPU_MX28 0x28
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#define MXC_CPU_MX31 0x31
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#define MXC_CPU_MX35 0x35
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#define MXC_CPU_MX51 0x51
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#define MXC_CPU_MX53 0x53
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#define MXC_CPU_MX6SL 0x60
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#define MXC_CPU_MX6DL 0x61
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#define MXC_CPU_MX6SX 0x62
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#define MXC_CPU_MX6Q 0x63
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#define MXC_CPU_MX6UL 0x64
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#define MXC_CPU_MX6ULL 0x65
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#define MXC_CPU_MX6ULZ 0x6B
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#define MXC_CPU_MX6SOLO 0x66 /* dummy */
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#define MXC_CPU_MX6SLL 0x67
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#define MXC_CPU_MX6D 0x6A
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#define MXC_CPU_MX6DP 0x68
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#define MXC_CPU_MX6QP 0x69
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#define MXC_CPU_MX7S 0x71 /* dummy ID */
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#define MXC_CPU_MX7D 0x72
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#define MXC_CPU_IMX8MQ 0x82
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#define MXC_CPU_IMX8MD 0x83 /* dummy ID */
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#define MXC_CPU_IMX8MQL 0x84 /* dummy ID */
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#define MXC_CPU_IMX8MM 0x85 /* dummy ID */
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#define MXC_CPU_IMX8MML 0x86 /* dummy ID */
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#define MXC_CPU_IMX8MMD 0x87 /* dummy ID */
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#define MXC_CPU_IMX8MMDL 0x88 /* dummy ID */
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#define MXC_CPU_IMX8MMS 0x89 /* dummy ID */
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#define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */
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#define MXC_CPU_IMX8MN 0x8b /* dummy ID */
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#define MXC_CPU_IMX8MND 0x8c /* dummy ID */
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#define MXC_CPU_IMX8MNS 0x8d /* dummy ID */
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#define MXC_CPU_IMX8MNL 0x8e /* dummy ID */
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#define MXC_CPU_IMX8MNDL 0x8f /* dummy ID */
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#define MXC_CPU_IMX8MNSL 0x181 /* dummy ID */
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#define MXC_CPU_IMX8MP 0x182/* dummy ID */
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#define MXC_CPU_IMX8MP7 0x183 /* dummy ID */
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#define MXC_CPU_IMX8MP6 0x184 /* dummy ID */
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#define MXC_CPU_IMX8MP5 0x185 /* dummy ID */
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#define MXC_CPU_IMX8MPL 0x186 /* dummy ID */
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#define MXC_CPU_IMX8MPD 0x187 /* dummy ID */
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#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
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#define MXC_CPU_IMX8QM 0x91 /* dummy ID */
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#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
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#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
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#define MXC_CPU_VF610 0xF6 /* dummy ID */
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#define MXC_SOC_MX6 0x60
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#define MXC_SOC_MX7 0x70
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#define MXC_SOC_IMX8M 0x80
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#define MXC_SOC_IMX8 0x90 /* dummy */
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#define MXC_SOC_MX7ULP 0xE0 /* dummy */
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#define CHIP_REV_1_0 0x10
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#define CHIP_REV_1_1 0x11
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#define CHIP_REV_1_2 0x12
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#define CHIP_REV_1_5 0x15
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#define CHIP_REV_2_0 0x20
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#define CHIP_REV_2_1 0x21
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#define CHIP_REV_2_5 0x25
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#define CHIP_REV_3_0 0x30
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#define CHIP_REV_A 0x0
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#define CHIP_REV_B 0x1
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#define CHIP_REV_C 0x2
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#define BOARD_REV_1_0 0x0
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#define BOARD_REV_2_0 0x1
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#define BOARD_VER_OFFSET 0x8
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#define CS0_128 0
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#define CS0_64M_CS1_64M 1
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#define CS0_64M_CS1_32M_CS2_32M 2
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#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
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u32 get_imx_reset_cause(void);
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ulong get_systemPLLCLK(void);
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ulong get_FCLK(void);
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ulong get_HCLK(void);
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ulong get_BCLK(void);
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ulong get_PERCLK1(void);
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ulong get_PERCLK2(void);
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ulong get_PERCLK3(void);
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