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![Vipul Kumar](/assets/img/avatar_default.png)
This patch replaced "return 0" with "return status" to fix the incorrect return value error reported by the coverity. Reviewed-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> [jagan: rebased on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
630 lines
16 KiB
C
630 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2013 Xilinx, Inc.
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* (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
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*
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* Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
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*/
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#include <common.h>
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#include <dm.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
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#define ZYNQ_QSPI_CR_IFMODE_MASK BIT(31) /* Flash intrface mode*/
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#define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */
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#define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */
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#define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */
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#define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */
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#define ZYNQ_QSPI_CR_SS_MASK GENMASK(13, 10) /* Slave Select */
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#define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
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#define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */
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#define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
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#define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */
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#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
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#define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
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#define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
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#define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
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#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
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/* zynq qspi Transmit Data Register */
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#define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
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#define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
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#define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
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#define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
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#define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/
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#define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */
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#define ZYNQ_QSPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
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#define ZYNQ_QSPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
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#define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
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#define ZYNQ_QSPI_FIFO_DEPTH 63
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#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT
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#define CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
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#endif
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/* zynq qspi register set */
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struct zynq_qspi_regs {
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u32 cr; /* 0x00 */
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u32 isr; /* 0x04 */
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u32 ier; /* 0x08 */
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u32 idr; /* 0x0C */
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u32 imr; /* 0x10 */
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u32 enr; /* 0x14 */
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u32 dr; /* 0x18 */
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u32 txd0r; /* 0x1C */
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u32 drxr; /* 0x20 */
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u32 sicr; /* 0x24 */
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u32 txftr; /* 0x28 */
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u32 rxftr; /* 0x2C */
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u32 gpior; /* 0x30 */
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u32 reserved0[19];
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u32 txd1r; /* 0x80 */
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u32 txd2r; /* 0x84 */
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u32 txd3r; /* 0x88 */
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u32 reserved1[5];
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u32 lqspicfg; /* 0xA0 */
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u32 lqspists; /* 0xA4 */
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};
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/* zynq qspi platform data */
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struct zynq_qspi_platdata {
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struct zynq_qspi_regs *regs;
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u32 frequency; /* input frequency */
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u32 speed_hz;
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};
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/* zynq qspi priv */
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struct zynq_qspi_priv {
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struct zynq_qspi_regs *regs;
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u8 cs;
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u8 mode;
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u8 fifo_depth;
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u32 freq; /* required frequency */
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const void *tx_buf;
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void *rx_buf;
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unsigned len;
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int bytes_to_transfer;
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int bytes_to_receive;
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unsigned int is_inst;
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unsigned cs_change:1;
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};
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static int zynq_qspi_ofdata_to_platdata(struct udevice *bus)
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{
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struct zynq_qspi_platdata *plat = bus->platdata;
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const void *blob = gd->fdt_blob;
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int node = dev_of_offset(bus);
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plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
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node, "reg");
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/* FIXME: Use 166MHz as a suitable default */
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plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
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166666666);
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plat->speed_hz = plat->frequency / 2;
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debug("%s: regs=%p max-frequency=%d\n", __func__,
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plat->regs, plat->frequency);
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return 0;
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}
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static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
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{
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struct zynq_qspi_regs *regs = priv->regs;
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u32 confr;
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/* Disable QSPI */
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writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
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/* Disable Interrupts */
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writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr);
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/* Clear the TX and RX threshold reg */
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writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, ®s->txftr);
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writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, ®s->rxftr);
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/* Clear the RX FIFO */
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while (readl(®s->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
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readl(®s->drxr);
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/* Clear Interrupts */
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writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->isr);
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/* Manual slave select and Auto start */
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confr = readl(®s->cr);
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confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
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confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
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ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
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ZYNQ_QSPI_CR_MSTREN_MASK;
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writel(confr, ®s->cr);
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/* Disable the LQSPI feature */
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confr = readl(®s->lqspicfg);
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confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
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writel(confr, ®s->lqspicfg);
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/* Enable SPI */
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writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
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}
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static int zynq_qspi_probe(struct udevice *bus)
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{
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struct zynq_qspi_platdata *plat = dev_get_platdata(bus);
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struct zynq_qspi_priv *priv = dev_get_priv(bus);
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priv->regs = plat->regs;
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priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
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/* init the zynq spi hw */
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zynq_qspi_init_hw(priv);
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return 0;
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}
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/*
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* zynq_qspi_read_data - Copy data to RX buffer
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* @zqspi: Pointer to the zynq_qspi structure
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* @data: The 32 bit variable where data is stored
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* @size: Number of bytes to be copied from data to RX buffer
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*/
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static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size)
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{
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u8 byte3;
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debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
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data, (unsigned)(priv->rx_buf), size);
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if (priv->rx_buf) {
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switch (size) {
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case 1:
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*((u8 *)priv->rx_buf) = data;
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priv->rx_buf += 1;
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break;
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case 2:
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*((u16 *)priv->rx_buf) = data;
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priv->rx_buf += 2;
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break;
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case 3:
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*((u16 *)priv->rx_buf) = data;
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priv->rx_buf += 2;
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byte3 = (u8)(data >> 16);
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*((u8 *)priv->rx_buf) = byte3;
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priv->rx_buf += 1;
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break;
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case 4:
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/* Can not assume word aligned buffer */
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memcpy(priv->rx_buf, &data, size);
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priv->rx_buf += 4;
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break;
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default:
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/* This will never execute */
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break;
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}
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}
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priv->bytes_to_receive -= size;
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if (priv->bytes_to_receive < 0)
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priv->bytes_to_receive = 0;
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}
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/*
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* zynq_qspi_write_data - Copy data from TX buffer
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* @zqspi: Pointer to the zynq_qspi structure
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* @data: Pointer to the 32 bit variable where data is to be copied
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* @size: Number of bytes to be copied from TX buffer to data
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*/
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static void zynq_qspi_write_data(struct zynq_qspi_priv *priv,
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u32 *data, u8 size)
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{
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if (priv->tx_buf) {
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switch (size) {
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case 1:
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*data = *((u8 *)priv->tx_buf);
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priv->tx_buf += 1;
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*data |= 0xFFFFFF00;
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break;
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case 2:
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*data = *((u16 *)priv->tx_buf);
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priv->tx_buf += 2;
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*data |= 0xFFFF0000;
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break;
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case 3:
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*data = *((u16 *)priv->tx_buf);
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priv->tx_buf += 2;
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*data |= (*((u8 *)priv->tx_buf) << 16);
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priv->tx_buf += 1;
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*data |= 0xFF000000;
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break;
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case 4:
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/* Can not assume word aligned buffer */
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memcpy(data, priv->tx_buf, size);
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priv->tx_buf += 4;
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break;
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default:
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/* This will never execute */
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break;
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}
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} else {
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*data = 0;
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}
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debug("%s: data 0x%08x tx_buf addr: 0x%08x size %d\n", __func__,
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*data, (u32)priv->tx_buf, size);
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priv->bytes_to_transfer -= size;
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if (priv->bytes_to_transfer < 0)
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priv->bytes_to_transfer = 0;
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}
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static void zynq_qspi_chipselect(struct zynq_qspi_priv *priv, int is_on)
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{
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u32 confr;
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struct zynq_qspi_regs *regs = priv->regs;
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confr = readl(®s->cr);
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if (is_on) {
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/* Select the slave */
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confr &= ~ZYNQ_QSPI_CR_SS_MASK;
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confr |= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) &
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ZYNQ_QSPI_CR_SS_MASK;
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} else
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/* Deselect the slave */
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confr |= ZYNQ_QSPI_CR_SS_MASK;
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writel(confr, ®s->cr);
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}
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/*
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* zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
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* @zqspi: Pointer to the zynq_qspi structure
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*/
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static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size)
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{
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u32 data = 0;
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u32 fifocount = 0;
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unsigned len, offset;
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struct zynq_qspi_regs *regs = priv->regs;
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static const unsigned offsets[4] = {
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ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
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ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };
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while ((fifocount < size) &&
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(priv->bytes_to_transfer > 0)) {
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if (priv->bytes_to_transfer >= 4) {
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if (priv->tx_buf) {
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memcpy(&data, priv->tx_buf, 4);
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priv->tx_buf += 4;
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} else {
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data = 0;
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}
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writel(data, ®s->txd0r);
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priv->bytes_to_transfer -= 4;
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fifocount++;
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} else {
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/* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */
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if (!(readl(®s->isr)
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& ZYNQ_QSPI_IXR_TXOW_MASK) &&
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!priv->rx_buf)
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return;
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len = priv->bytes_to_transfer;
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zynq_qspi_write_data(priv, &data, len);
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offset = (priv->rx_buf) ? offsets[0] : offsets[len];
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writel(data, ®s->cr + (offset / 4));
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}
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}
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}
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/*
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* zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller
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* @zqspi: Pointer to the zynq_qspi structure
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*
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* This function handles TX empty and Mode Fault interrupts only.
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* On TX empty interrupt this function reads the received data from RX FIFO and
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* fills the TX FIFO if there is any data remaining to be transferred.
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* On Mode Fault interrupt this function indicates that transfer is completed,
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* the SPI subsystem will identify the error as the remaining bytes to be
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* transferred is non-zero.
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*
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* returns: 0 for poll timeout
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* 1 transfer operation complete
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*/
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static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
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{
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struct zynq_qspi_regs *regs = priv->regs;
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u32 rxindex = 0;
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u32 rxcount;
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u32 status, timeout;
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/* Poll until any of the interrupt status bits are set */
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timeout = get_timer(0);
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do {
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status = readl(®s->isr);
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} while ((status == 0) &&
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(get_timer(timeout) < CONFIG_SYS_ZYNQ_QSPI_WAIT));
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if (status == 0) {
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printf("zynq_qspi_irq_poll: Timeout!\n");
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return -ETIMEDOUT;
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}
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writel(status, ®s->isr);
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/* Disable all interrupts */
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writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr);
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if ((status & ZYNQ_QSPI_IXR_TXOW_MASK) ||
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(status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)) {
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/*
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* This bit is set when Tx FIFO has < THRESHOLD entries. We have
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* the THRESHOLD value set to 1, so this bit indicates Tx FIFO
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* is empty
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*/
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rxcount = priv->bytes_to_receive - priv->bytes_to_transfer;
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rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4);
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while ((rxindex < rxcount) &&
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(rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) {
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/* Read out the data from the RX FIFO */
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u32 data;
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data = readl(®s->drxr);
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if (priv->bytes_to_receive >= 4) {
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if (priv->rx_buf) {
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memcpy(priv->rx_buf, &data, 4);
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priv->rx_buf += 4;
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}
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priv->bytes_to_receive -= 4;
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} else {
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zynq_qspi_read_data(priv, data,
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priv->bytes_to_receive);
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}
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rxindex++;
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}
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if (priv->bytes_to_transfer) {
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/* There is more data to send */
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zynq_qspi_fill_tx_fifo(priv,
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ZYNQ_QSPI_RXFIFO_THRESHOLD);
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writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier);
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} else {
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/*
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* If transfer and receive is completed then only send
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* complete signal
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*/
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if (!priv->bytes_to_receive) {
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/* return operation complete */
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writel(ZYNQ_QSPI_IXR_ALL_MASK,
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®s->idr);
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return 1;
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}
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}
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}
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return 0;
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}
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/*
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* zynq_qspi_start_transfer - Initiates the QSPI transfer
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* @qspi: Pointer to the spi_device structure
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* @transfer: Pointer to the spi_transfer structure which provide information
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* about next transfer parameters
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*
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* This function fills the TX FIFO, starts the QSPI transfer, and waits for the
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* transfer to be completed.
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*
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* returns: Number of bytes transferred in the last transfer
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*/
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static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv)
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{
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u32 data = 0;
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struct zynq_qspi_regs *regs = priv->regs;
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debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__,
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(u32)priv, (u32)priv, priv->len);
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priv->bytes_to_transfer = priv->len;
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priv->bytes_to_receive = priv->len;
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if (priv->len < 4)
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zynq_qspi_fill_tx_fifo(priv, priv->len);
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else
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zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth);
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writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier);
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/* wait for completion */
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do {
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data = zynq_qspi_irq_poll(priv);
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} while (data == 0);
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return (priv->len) - (priv->bytes_to_transfer);
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}
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static int zynq_qspi_transfer(struct zynq_qspi_priv *priv)
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{
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unsigned cs_change = 1;
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int status = 0;
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while (1) {
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/* Select the chip if required */
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if (cs_change)
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zynq_qspi_chipselect(priv, 1);
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cs_change = priv->cs_change;
|
|
|
|
if (!priv->tx_buf && !priv->rx_buf && priv->len) {
|
|
status = -1;
|
|
break;
|
|
}
|
|
|
|
/* Request the transfer */
|
|
if (priv->len) {
|
|
status = zynq_qspi_start_transfer(priv);
|
|
priv->is_inst = 0;
|
|
}
|
|
|
|
if (status != priv->len) {
|
|
if (status > 0)
|
|
status = -EMSGSIZE;
|
|
debug("zynq_qspi_transfer:%d len:%d\n",
|
|
status, priv->len);
|
|
break;
|
|
}
|
|
status = 0;
|
|
|
|
if (cs_change)
|
|
/* Deselect the chip */
|
|
zynq_qspi_chipselect(priv, 0);
|
|
|
|
break;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
static int zynq_qspi_claim_bus(struct udevice *dev)
|
|
{
|
|
struct udevice *bus = dev->parent;
|
|
struct zynq_qspi_priv *priv = dev_get_priv(bus);
|
|
struct zynq_qspi_regs *regs = priv->regs;
|
|
|
|
writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int zynq_qspi_release_bus(struct udevice *dev)
|
|
{
|
|
struct udevice *bus = dev->parent;
|
|
struct zynq_qspi_priv *priv = dev_get_priv(bus);
|
|
struct zynq_qspi_regs *regs = priv->regs;
|
|
|
|
writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen,
|
|
const void *dout, void *din, unsigned long flags)
|
|
{
|
|
struct udevice *bus = dev->parent;
|
|
struct zynq_qspi_priv *priv = dev_get_priv(bus);
|
|
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
|
|
|
|
priv->cs = slave_plat->cs;
|
|
priv->tx_buf = dout;
|
|
priv->rx_buf = din;
|
|
priv->len = bitlen / 8;
|
|
|
|
debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
|
|
bus->seq, slave_plat->cs, bitlen, priv->len, flags);
|
|
|
|
/*
|
|
* Festering sore.
|
|
* Assume that the beginning of a transfer with bits to
|
|
* transmit must contain a device command.
|
|
*/
|
|
if (dout && flags & SPI_XFER_BEGIN)
|
|
priv->is_inst = 1;
|
|
else
|
|
priv->is_inst = 0;
|
|
|
|
if (flags & SPI_XFER_END)
|
|
priv->cs_change = 1;
|
|
else
|
|
priv->cs_change = 0;
|
|
|
|
zynq_qspi_transfer(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
|
|
{
|
|
struct zynq_qspi_platdata *plat = bus->platdata;
|
|
struct zynq_qspi_priv *priv = dev_get_priv(bus);
|
|
struct zynq_qspi_regs *regs = priv->regs;
|
|
uint32_t confr;
|
|
u8 baud_rate_val = 0;
|
|
|
|
if (speed > plat->frequency)
|
|
speed = plat->frequency;
|
|
|
|
/* Set the clock frequency */
|
|
confr = readl(®s->cr);
|
|
if (speed == 0) {
|
|
/* Set baudrate x8, if the freq is 0 */
|
|
baud_rate_val = 0x2;
|
|
} else if (plat->speed_hz != speed) {
|
|
while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) &&
|
|
((plat->frequency /
|
|
(2 << baud_rate_val)) > speed))
|
|
baud_rate_val++;
|
|
|
|
plat->speed_hz = speed / (2 << baud_rate_val);
|
|
}
|
|
confr &= ~ZYNQ_QSPI_CR_BAUD_MASK;
|
|
confr |= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT);
|
|
|
|
writel(confr, ®s->cr);
|
|
priv->freq = speed;
|
|
|
|
debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
|
|
{
|
|
struct zynq_qspi_priv *priv = dev_get_priv(bus);
|
|
struct zynq_qspi_regs *regs = priv->regs;
|
|
uint32_t confr;
|
|
|
|
/* Set the SPI Clock phase and polarities */
|
|
confr = readl(®s->cr);
|
|
confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);
|
|
|
|
if (mode & SPI_CPHA)
|
|
confr |= ZYNQ_QSPI_CR_CPHA_MASK;
|
|
if (mode & SPI_CPOL)
|
|
confr |= ZYNQ_QSPI_CR_CPOL_MASK;
|
|
|
|
writel(confr, ®s->cr);
|
|
priv->mode = mode;
|
|
|
|
debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_spi_ops zynq_qspi_ops = {
|
|
.claim_bus = zynq_qspi_claim_bus,
|
|
.release_bus = zynq_qspi_release_bus,
|
|
.xfer = zynq_qspi_xfer,
|
|
.set_speed = zynq_qspi_set_speed,
|
|
.set_mode = zynq_qspi_set_mode,
|
|
};
|
|
|
|
static const struct udevice_id zynq_qspi_ids[] = {
|
|
{ .compatible = "xlnx,zynq-qspi-1.0" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(zynq_qspi) = {
|
|
.name = "zynq_qspi",
|
|
.id = UCLASS_SPI,
|
|
.of_match = zynq_qspi_ids,
|
|
.ops = &zynq_qspi_ops,
|
|
.ofdata_to_platdata = zynq_qspi_ofdata_to_platdata,
|
|
.platdata_auto_alloc_size = sizeof(struct zynq_qspi_platdata),
|
|
.priv_auto_alloc_size = sizeof(struct zynq_qspi_priv),
|
|
.probe = zynq_qspi_probe,
|
|
};
|