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https://github.com/brain-hackers/u-boot-brain
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![Wolfgang Denk](/assets/img/avatar_default.png)
* 'master' of git://git.denx.de/u-boot-arm: ARM: Add Calxeda Highbank platform dkb: make mmc command as default enabled Marvell: dkb: add mmc support ARM: pantheon: add mmc definition davinci: remove config.mk file from the sources ARM:AM33XX: Add support for TI AM335X EVM ARM:AM33XX: Added timer support ARM:AM33XX: Add emif/ddr support ARM:AM33XX: Add clock definitions ARM:AM33XX: Added support for AM33xx omap3/emif4: fix registers definition davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM davinci: emac: add support for more than 1 PHYs davinci: emac: add new features to autonegotiate for EMAC da850evm: Move LPSC configuration to board_early_init_f() omap4_panda: Build in cmd_gpio support on panda omap: Don't use gpio_free to change direction to input mmc: omap: Allow OMAP_HSMMC[23]_BASE to be unset OMAP3: overo : Add environment variable optargs to bootargs OMAP3: overo: Move ethernet CS4 configuration to execute based on board id OMAP3: overo : Use ttyO2 instead of ttyS2. da830: add support for NAND boot mode dm36x: revert cache disable patch dm644X: revert cache disable patch devkit8000: Add malloc space omap: spl: fix build break due to changes in FAT OMAP3 SPL: Provide weak omap_rev_string omap: beagle: Use ubifs instead of jffs2 for nand boot omap: overo: Disable pull-ups on camera PCLK, HS and VS signals omap: overo: Configure mux for gpio10 SPL: Add DMA library omap3: Add interface for omap3 DMA omap3: Add DMA register accessors omap3: Add Base register for DMA arm, davinci: add missing LSPC define for MMC/SD1 U-Boot/SPL: omap4: Make ddr pre-calculated timings as default. DaVinci: correct MDSTAT.STATE mask omap4: splitting padconfs into common, 4430 and 4460 omap4: adding revision detection for 4460 ES1.1 omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROL gplug: fixed build error as a result of code cleanup patch kirkwood_spi: add dummy spi_init() gpio: mvmfp: reduce include platform file ARM: orion5x: reduce dependence of including platform file serial: reduce include platform file for marvell chip ARM: kirkwood: reduce dependence of including platform file ARM: armada100: reduce dependence of including platform file ARM: pantheon: reduce dependence of including platform file Armada100: Add env storage support for Marvell gplugD Armada100: Add SPI flash support for Marvell gplugD Armada100: Add SPI support for Marvell gplugD SPI: Add SPI driver support for Marvell Armada100 dreamplug: initial board support. imx: fix coding style misc: pmic: drop old Freescale's pmic driver MX31: mx31pdk: use new pmic driver MX31: mx31ads: use new pmic driver MX31: mx31_litekit: use new pmic driver MX5: mx53evk: use new pmic driver MX5: mx51evk: use new pmic driver MX35: mx35pdk: use new pmic driver misc: pmic: addI2C support to pmic_fsl driver misc: pmic: use I2C_SET_BUS in pmic I2C MX5: efikamx/efikasb: use new pmic driver MX3: qong: use new pmic driver RTC: Switch mc13783 to generic pmic code MX5: vision2: use new pmic driver misc: pmic: Freescale PMIC switches to generic PMIC driver misc:pmic:samsung Enable PMIC driver at GONI target misc:pmic:max8998 MAX8998 support at a new PMIC driver. misc:pmic:core New generic PMIC driver mx31pdk: Remove unneeded config mx31: provide readable WEIM CS accessor MX51: vision2: Set global macros I2C: Add i2c_get/set_speed() to mxc_i2c.c ARM: Update mach-types devkit8000: Add config to enable SPL MMC boot devkit8000: protect board_mmc_init arm, post: add missing post_time_ms for arm cosmetic, post: Codingstyle cleanup arm, logbuffer: make it compileclean tegra2: Enable MMC for Seaboard tegra2: Add more pinmux functions tegra2: Rename PIN_ to PINGRP_ tegra2: Add more clock functions tegra2: Clean up board code a little tegra2: Rename CLOCK_PLL_ID to CLOCK_ID
170 lines
4.7 KiB
C
170 lines
4.7 KiB
C
/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <s6e63d6.h>
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#include <netdev.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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int board_init(void)
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{
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gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */
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gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
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return 0;
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}
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int board_early_init_f(void)
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{
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/* CS0: Nor Flash */
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static const struct mxc_weimcs cs0 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
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};
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/* CS1: Network Controller */
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static const struct mxc_weimcs cs1 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
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};
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/* CS4: SRAM */
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static const struct mxc_weimcs cs4 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
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};
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mxc_setup_weimcs(0, &cs0);
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mxc_setup_weimcs(1, &cs1);
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mxc_setup_weimcs(4, &cs4);
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/* setup pins for UART1 */
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mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
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mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
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mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
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mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
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/* setup pins for I2C2 (for EEPROM, RTC) */
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mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
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mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA);
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_S6E63D6
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struct s6e63d6 data = {
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/*
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* See comment in mxc_spi.c::decode_cs() for .cs field format.
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* We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
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* 2 of the SPI controller #1, since it is unused.
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*/
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.cs = 2 | (57 << 8),
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.bus = 0,
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.id = 0,
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};
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int ret;
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/* SPI1 */
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mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
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mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
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mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
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mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
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mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
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mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
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mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
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/* start SPI1 clock */
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__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
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/* GPIO 57 */
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/* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
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mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
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/* SPI1 CS2 is free */
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ret = s6e63d6_init(&data);
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if (ret)
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return ret;
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/*
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* This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
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* OLED display connected to a S6E63D6 SPI display controller in the
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* 18 bit RGB mode
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*/
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s6e63d6_index(&data, 2);
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s6e63d6_param(&data, 0x0182);
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s6e63d6_index(&data, 3);
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s6e63d6_param(&data, 0x8130);
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s6e63d6_index(&data, 0x10);
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s6e63d6_param(&data, 0x0000);
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s6e63d6_index(&data, 5);
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s6e63d6_param(&data, 0x0001);
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s6e63d6_index(&data, 0x22);
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#endif
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return 0;
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}
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#endif
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int checkboard (void)
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{
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printf("Board: Phytec phyCore i.MX31\n");
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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