mirror of
https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
This is a better name for this protocol. Also remove the typedef to keep checkpatch happy, and move zeroing of NetBootFileXferSize a little earlier since TFTPPUT will need to change this. Signed-off-by: Simon Glass <sjg@chromium.org>
404 lines
9.8 KiB
C
404 lines
9.8 KiB
C
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* hacked for Hymod FPGA support by Murray.Jensen@csiro.au, 29-Jan-01
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*/
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#include <common.h>
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#include <command.h>
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#include <net.h>
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#include <asm/iopin_8260.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*-----------------------------------------------------------------------
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* Board Special Commands: FPGA load/store, EEPROM erase
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*/
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#if defined(CONFIG_CMD_BSP)
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#define LOAD_SUCCESS 0
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#define LOAD_FAIL_NOCONF 1
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#define LOAD_FAIL_NOINIT 2
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#define LOAD_FAIL_NODONE 3
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#define STORE_SUCCESS 0
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/*
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* Programming the Hymod FPGAs
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*
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* The 8260 io port config table is set up so that the INIT pin is
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* held Low (Open Drain output 0) - this will delay the automatic
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* Power-On config until INIT is released (by making it an input).
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*
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* If the FPGA has been programmed before, then the assertion of PROGRAM
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* will initiate configuration (i.e. it begins clearing the RAM).
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*
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* When the FPGA is ready to receive configuration data (either after
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* releasing INIT after Power-On, or after asserting PROGRAM), it will
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* pull INIT high.
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*
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* Notes from Paul Dunn:
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*
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* 1. program pin should be forced low for >= 300ns
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* (about 20 bus clock cycles minimum).
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*
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* 2. then wait for init to go high, which signals
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* that the FPGA has cleared its internal memory
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* and is ready to load
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*
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* 3. perform load writes of entire config file
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*
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* 4. wait for done to go high, which should be
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* within a few bus clock cycles. If done has not
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* gone high after reasonable period, then load
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* has not worked (wait several ms?)
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*/
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int
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fpga_load(int mezz, const uchar *addr, ulong size)
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{
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hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
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xlx_info_t *fp;
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xlx_iopins_t *fpgaio;
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volatile uchar *fpgabase;
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volatile uint cnt;
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const uchar *eaddr = addr + size;
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int result;
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if (mezz)
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fp = &cp->mezz.xlx[0];
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else
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fp = &cp->main.xlx[0];
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if (!fp->mmap.prog.exists)
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return (LOAD_FAIL_NOCONF);
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fpgabase = (uchar *)fp->mmap.prog.base;
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fpgaio = &fp->iopins;
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/* set enable HIGH if required */
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if (fpgaio->enable_pin.flag)
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iopin_set_high (&fpgaio->enable_pin);
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/* ensure INIT is released (set it to be an input) */
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iopin_set_in (&fpgaio->init_pin);
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/* toggle PROG Low then High (will already be Low after Power-On) */
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iopin_set_low (&fpgaio->prog_pin);
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udelay (1); /* minimum 300ns - 1usec should do it */
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iopin_set_high (&fpgaio->prog_pin);
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/* wait for INIT High */
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cnt = 0;
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while (!iopin_is_high (&fpgaio->init_pin))
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if (++cnt == 10000000) {
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result = LOAD_FAIL_NOINIT;
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goto done;
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}
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/* write configuration data */
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while (addr < eaddr)
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*fpgabase = *addr++;
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/* wait for DONE High */
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cnt = 0;
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while (!iopin_is_high (&fpgaio->done_pin))
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if (++cnt == 100000000) {
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result = LOAD_FAIL_NODONE;
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goto done;
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}
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/* success */
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result = LOAD_SUCCESS;
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done:
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if (fpgaio->enable_pin.flag)
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iopin_set_low (&fpgaio->enable_pin);
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return (result);
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}
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/* ------------------------------------------------------------------------- */
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int
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do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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uchar *addr, *save_addr;
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ulong size;
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int mezz, arg, result;
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switch (argc) {
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case 0:
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case 1:
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break;
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case 2:
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if (strcmp (argv[1], "info") == 0) {
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printf ("\nHymod FPGA Info...\n");
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printf ("\t\t\t\tAddress\t\tSize\n");
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printf ("\tMain Configuration:\t0x%08x\t%d\n",
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FPGA_MAIN_CFG_BASE, FPGA_MAIN_CFG_SIZE);
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printf ("\tMain Register:\t\t0x%08x\t%d\n",
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FPGA_MAIN_REG_BASE, FPGA_MAIN_REG_SIZE);
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printf ("\tMain Port:\t\t0x%08x\t%d\n",
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FPGA_MAIN_PORT_BASE, FPGA_MAIN_PORT_SIZE);
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printf ("\tMezz Configuration:\t0x%08x\t%d\n",
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FPGA_MEZZ_CFG_BASE, FPGA_MEZZ_CFG_SIZE);
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return 0;
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}
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break;
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case 3:
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if (strcmp (argv[1], "store") == 0) {
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addr = (uchar *) simple_strtoul (argv[2], NULL, 16);
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save_addr = addr;
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#if 0
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/* fpga readback unimplemented */
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while (more readback data)
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*addr++ = *fpga;
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result = error ? STORE_FAIL_XXX : STORE_SUCCESS;
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#else
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result = STORE_SUCCESS;
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#endif
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if (result == STORE_SUCCESS) {
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printf ("SUCCEEDED (%d bytes)\n",
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addr - save_addr);
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return 0;
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} else
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printf ("FAILED (%d bytes)\n",
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addr - save_addr);
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return 1;
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}
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break;
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case 4:
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if (strcmp (argv[1], "tftp") == 0) {
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copy_filename (BootFile, argv[2], sizeof (BootFile));
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load_addr = simple_strtoul (argv[3], NULL, 16);
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NetBootFileXferSize = 0;
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if (NetLoop(TFTPGET) <= 0) {
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printf ("tftp transfer failed - aborting "
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"fgpa load\n");
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return 1;
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}
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if (NetBootFileXferSize == 0) {
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printf ("can't determine file size - "
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"aborting fpga load\n");
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return 1;
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}
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printf ("File transfer succeeded - "
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"beginning fpga load...");
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result = fpga_load (0, (uchar *) load_addr,
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NetBootFileXferSize);
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if (result == LOAD_SUCCESS) {
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printf ("SUCCEEDED\n");
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return 0;
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} else if (result == LOAD_FAIL_NOCONF)
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printf ("FAILED (no CONF)\n");
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else if (result == LOAD_FAIL_NOINIT)
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printf ("FAILED (no INIT)\n");
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else
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printf ("FAILED (no DONE)\n");
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return 1;
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}
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/* fall through ... */
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case 5:
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if (strcmp (argv[1], "load") == 0) {
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if (argc == 5) {
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if (strcmp (argv[2], "main") == 0)
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mezz = 0;
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else if (strcmp (argv[2], "mezz") == 0)
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mezz = 1;
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else {
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printf ("FPGA type must be either "
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"`main' or `mezz'\n");
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return 1;
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}
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arg = 3;
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} else {
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mezz = 0;
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arg = 2;
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}
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addr = (uchar *) simple_strtoul (argv[arg++], NULL, 16);
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size = (ulong) simple_strtoul (argv[arg], NULL, 16);
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result = fpga_load (mezz, addr, size);
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if (result == LOAD_SUCCESS) {
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printf ("SUCCEEDED\n");
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return 0;
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} else if (result == LOAD_FAIL_NOCONF)
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printf ("FAILED (no CONF)\n");
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else if (result == LOAD_FAIL_NOINIT)
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printf ("FAILED (no INIT)\n");
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else
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printf ("FAILED (no DONE)\n");
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return 1;
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}
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break;
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default:
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break;
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}
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return cmd_usage(cmdtp);
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}
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U_BOOT_CMD(
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fpga, 6, 1, do_fpga,
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"FPGA sub-system",
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"load [type] addr size\n"
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" - write the configuration data at memory address `addr',\n"
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" size `size' bytes, into the FPGA of type `type' (either\n"
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" `main' or `mezz', default `main'). e.g.\n"
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" `fpga load 100000 7d8f'\n"
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" loads the main FPGA with config data at address 100000\n"
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" HEX, size 7d8f HEX (32143 DEC) bytes\n"
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"fpga tftp file addr\n"
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" - transfers `file' from the tftp server into memory at\n"
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" address `addr', then writes the entire file contents\n"
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" into the main FPGA\n"
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"fpga store addr\n"
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" - read configuration data from the main FPGA (the mezz\n"
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" FPGA is write-only), into address `addr'. There must be\n"
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" enough memory available at `addr' to hold all the config\n"
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" data - the size of which is determined by VC:???\n"
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"fpga info\n"
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" - print information about the Hymod FPGA, namely the\n"
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" memory addresses at which the four FPGA local bus\n"
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" address spaces appear in the physical address space"
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);
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/* ------------------------------------------------------------------------- */
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int
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do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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uchar data[HYMOD_EEPROM_SIZE];
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uint addr = CONFIG_SYS_I2C_EEPROM_ADDR;
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switch (argc) {
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case 1:
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addr |= HYMOD_EEOFF_MAIN;
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break;
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case 2:
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if (strcmp (argv[1], "main") == 0) {
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addr |= HYMOD_EEOFF_MAIN;
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break;
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}
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if (strcmp (argv[1], "mezz") == 0) {
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addr |= HYMOD_EEOFF_MEZZ;
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break;
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}
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/* fall through ... */
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default:
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return cmd_usage(cmdtp);
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}
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memset (data, 0, HYMOD_EEPROM_SIZE);
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eeprom_write (addr, 0, data, HYMOD_EEPROM_SIZE);
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return 0;
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}
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U_BOOT_CMD(
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eeclear, 1, 0, do_eecl,
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"Clear the eeprom on a Hymod board",
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"[type]\n"
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" - write zeroes into the EEPROM on the board of type `type'\n"
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" (`type' is either `main' or `mezz' - default `main')\n"
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" Note: the EEPROM write enable jumper must be installed"
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);
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/* ------------------------------------------------------------------------- */
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int
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do_htest (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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#if 0
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int rc;
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#endif
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#ifdef CONFIG_ETHER_LOOPBACK_TEST
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extern void eth_loopback_test (void);
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#endif /* CONFIG_ETHER_LOOPBACK_TEST */
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printf ("HYMOD tests - ensure loopbacks etc. are connected\n\n");
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#if 0
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/* Load FPGA with test program */
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printf ("Loading test FPGA program ...");
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rc = fpga_load (0, test_bitfile, sizeof (test_bitfile));
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switch (rc) {
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case LOAD_SUCCESS:
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printf (" SUCCEEDED\n");
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break;
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case LOAD_FAIL_NOCONF:
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printf (" FAILED (no configuration space defined)\n");
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return 1;
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case LOAD_FAIL_NOINIT:
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printf (" FAILED (timeout - no INIT signal seen)\n");
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return 1;
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case LOAD_FAIL_NODONE:
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printf (" FAILED (timeout - no DONE signal seen)\n");
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return 1;
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default:
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printf (" FAILED (unknown return code from fpga_load\n");
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return 1;
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}
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/* run Local Bus <=> Xilinx tests */
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/* tell Xilinx to run ZBT Ram, High Speed serial and Mezzanine tests */
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/* run SDRAM test */
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#endif
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#ifdef CONFIG_ETHER_LOOPBACK_TEST
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/* run Ethernet test */
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eth_loopback_test ();
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#endif /* CONFIG_ETHER_LOOPBACK_TEST */
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return 0;
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}
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#endif
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