mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-30 13:58:51 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
849 lines
20 KiB
C
849 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2010
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*/
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/*
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* Designware ethernet IP driver for U-Boot
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <miiphy.h>
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#include <malloc.h>
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#include <pci.h>
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#include <linux/compiler.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <asm/io.h>
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#include <power/regulator.h>
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#include "designware.h"
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static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
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{
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#ifdef CONFIG_DM_ETH
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struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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#else
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struct eth_mac_regs *mac_p = bus->priv;
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#endif
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ulong start;
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u16 miiaddr;
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int timeout = CONFIG_MDIO_TIMEOUT;
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miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
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((reg << MIIREGSHIFT) & MII_REGMSK);
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writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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if (!(readl(&mac_p->miiaddr) & MII_BUSY))
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return readl(&mac_p->miidata);
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udelay(10);
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};
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return -ETIMEDOUT;
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}
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static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
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u16 val)
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{
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#ifdef CONFIG_DM_ETH
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struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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#else
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struct eth_mac_regs *mac_p = bus->priv;
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#endif
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ulong start;
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u16 miiaddr;
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int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
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writel(val, &mac_p->miidata);
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miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
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((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
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writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
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ret = 0;
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break;
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}
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udelay(10);
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};
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return ret;
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}
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#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
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static int dw_mdio_reset(struct mii_dev *bus)
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{
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struct udevice *dev = bus->priv;
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struct dw_eth_dev *priv = dev_get_priv(dev);
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struct dw_eth_pdata *pdata = dev_get_platdata(dev);
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int ret;
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if (!dm_gpio_is_valid(&priv->reset_gpio))
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return 0;
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/* reset the phy */
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ret = dm_gpio_set_value(&priv->reset_gpio, 0);
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if (ret)
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return ret;
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udelay(pdata->reset_delays[0]);
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ret = dm_gpio_set_value(&priv->reset_gpio, 1);
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if (ret)
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return ret;
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udelay(pdata->reset_delays[1]);
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ret = dm_gpio_set_value(&priv->reset_gpio, 0);
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if (ret)
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return ret;
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udelay(pdata->reset_delays[2]);
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return 0;
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}
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#endif
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static int dw_mdio_init(const char *name, void *priv)
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{
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate MDIO bus\n");
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return -ENOMEM;
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}
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bus->read = dw_mdio_read;
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bus->write = dw_mdio_write;
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snprintf(bus->name, sizeof(bus->name), "%s", name);
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#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
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bus->reset = dw_mdio_reset;
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#endif
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bus->priv = priv;
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return mdio_register(bus);
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}
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static void tx_descs_init(struct dw_eth_dev *priv)
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{
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
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char *txbuffs = &priv->txbuffs[0];
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struct dmamacdescr *desc_p;
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u32 idx;
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for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
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desc_p = &desc_table_p[idx];
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desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
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desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
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#if defined(CONFIG_DW_ALTDESCRIPTOR)
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desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
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DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
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DESC_TXSTS_TXCHECKINSCTRL |
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DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
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desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
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desc_p->dmamac_cntl = 0;
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desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
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#else
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desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
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desc_p->txrx_status = 0;
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#endif
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}
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/* Correcting the last pointer of the chain */
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desc_p->dmamac_next = (ulong)&desc_table_p[0];
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/* Flush all Tx buffer descriptors at once */
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flush_dcache_range((ulong)priv->tx_mac_descrtable,
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(ulong)priv->tx_mac_descrtable +
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sizeof(priv->tx_mac_descrtable));
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writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
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priv->tx_currdescnum = 0;
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}
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static void rx_descs_init(struct dw_eth_dev *priv)
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{
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
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char *rxbuffs = &priv->rxbuffs[0];
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struct dmamacdescr *desc_p;
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u32 idx;
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/* Before passing buffers to GMAC we need to make sure zeros
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* written there right after "priv" structure allocation were
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* flushed into RAM.
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* Otherwise there's a chance to get some of them flushed in RAM when
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* GMAC is already pushing data to RAM via DMA. This way incoming from
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* GMAC data will be corrupted. */
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flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
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for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
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desc_p = &desc_table_p[idx];
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desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
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desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
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desc_p->dmamac_cntl =
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(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
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DESC_RXCTRL_RXCHAIN;
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desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
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}
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/* Correcting the last pointer of the chain */
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desc_p->dmamac_next = (ulong)&desc_table_p[0];
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/* Flush all Rx buffer descriptors at once */
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flush_dcache_range((ulong)priv->rx_mac_descrtable,
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(ulong)priv->rx_mac_descrtable +
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sizeof(priv->rx_mac_descrtable));
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writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
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priv->rx_currdescnum = 0;
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}
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static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
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{
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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u32 macid_lo, macid_hi;
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macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
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(mac_id[3] << 24);
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macid_hi = mac_id[4] + (mac_id[5] << 8);
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writel(macid_hi, &mac_p->macaddr0hi);
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writel(macid_lo, &mac_p->macaddr0lo);
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return 0;
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}
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static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
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struct phy_device *phydev)
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{
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u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
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if (!phydev->link) {
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printf("%s: No link.\n", phydev->dev->name);
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return 0;
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}
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if (phydev->speed != 1000)
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conf |= MII_PORTSELECT;
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else
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conf &= ~MII_PORTSELECT;
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if (phydev->speed == 100)
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conf |= FES_100;
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if (phydev->duplex)
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conf |= FULLDPLXMODE;
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writel(conf, &mac_p->conf);
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printf("Speed: %d, %s duplex%s\n", phydev->speed,
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(phydev->duplex) ? "full" : "half",
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(phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
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return 0;
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}
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static void _dw_eth_halt(struct dw_eth_dev *priv)
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{
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
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writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
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phy_shutdown(priv->phydev);
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}
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int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
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{
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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unsigned int start;
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int ret;
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writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
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start = get_timer(0);
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while (readl(&dma_p->busmode) & DMAMAC_SRST) {
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if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
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printf("DMA reset timeout\n");
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return -ETIMEDOUT;
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}
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mdelay(100);
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};
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/*
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* Soft reset above clears HW address registers.
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* So we have to set it here once again.
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*/
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_dw_write_hwaddr(priv, enetaddr);
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rx_descs_init(priv);
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tx_descs_init(priv);
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writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
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#ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
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writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
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&dma_p->opmode);
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#else
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writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
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&dma_p->opmode);
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#endif
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writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
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#ifdef CONFIG_DW_AXI_BURST_LEN
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writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
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#endif
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/* Start up the PHY */
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ret = phy_startup(priv->phydev);
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if (ret) {
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printf("Could not initialize PHY %s\n",
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priv->phydev->dev->name);
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return ret;
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}
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ret = dw_adjust_link(priv, mac_p, priv->phydev);
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if (ret)
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return ret;
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return 0;
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}
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int designware_eth_enable(struct dw_eth_dev *priv)
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{
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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if (!priv->phydev->link)
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return -EIO;
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writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
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return 0;
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}
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#define ETH_ZLEN 60
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static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
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{
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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u32 desc_num = priv->tx_currdescnum;
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struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
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ulong desc_start = (ulong)desc_p;
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ulong desc_end = desc_start +
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roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
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ulong data_start = desc_p->dmamac_addr;
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ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
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/*
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* Strictly we only need to invalidate the "txrx_status" field
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* for the following check, but on some platforms we cannot
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* invalidate only 4 bytes, so we flush the entire descriptor,
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* which is 16 bytes in total. This is safe because the
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* individual descriptors in the array are each aligned to
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* ARCH_DMA_MINALIGN and padded appropriately.
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*/
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invalidate_dcache_range(desc_start, desc_end);
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/* Check if the descriptor is owned by CPU */
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if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
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printf("CPU not owner of tx frame\n");
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return -EPERM;
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}
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length = max(length, ETH_ZLEN);
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memcpy((void *)data_start, packet, length);
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/* Flush data to be sent */
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flush_dcache_range(data_start, data_end);
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#if defined(CONFIG_DW_ALTDESCRIPTOR)
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desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
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desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) &
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DESC_TXCTRL_SIZE1MASK;
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desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
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desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
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#else
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desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) &
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DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
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DESC_TXCTRL_TXFIRST;
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desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
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#endif
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/* Flush modified buffer descriptor */
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flush_dcache_range(desc_start, desc_end);
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/* Test the wrap-around condition. */
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if (++desc_num >= CONFIG_TX_DESCR_NUM)
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desc_num = 0;
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priv->tx_currdescnum = desc_num;
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/* Start the transmission */
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writel(POLL_DATA, &dma_p->txpolldemand);
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return 0;
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}
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static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
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{
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u32 status, desc_num = priv->rx_currdescnum;
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struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
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int length = -EAGAIN;
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ulong desc_start = (ulong)desc_p;
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ulong desc_end = desc_start +
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roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
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ulong data_start = desc_p->dmamac_addr;
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ulong data_end;
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/* Invalidate entire buffer descriptor */
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invalidate_dcache_range(desc_start, desc_end);
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status = desc_p->txrx_status;
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/* Check if the owner is the CPU */
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if (!(status & DESC_RXSTS_OWNBYDMA)) {
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length = (status & DESC_RXSTS_FRMLENMSK) >>
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DESC_RXSTS_FRMLENSHFT;
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/* Invalidate received data */
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data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
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invalidate_dcache_range(data_start, data_end);
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*packetp = (uchar *)(ulong)desc_p->dmamac_addr;
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}
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return length;
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}
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static int _dw_free_pkt(struct dw_eth_dev *priv)
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{
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u32 desc_num = priv->rx_currdescnum;
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struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
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ulong desc_start = (ulong)desc_p;
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ulong desc_end = desc_start +
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roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
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/*
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* Make the current descriptor valid again and go to
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* the next one
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*/
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desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
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/* Flush only status field - others weren't changed */
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flush_dcache_range(desc_start, desc_end);
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/* Test the wrap-around condition. */
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if (++desc_num >= CONFIG_RX_DESCR_NUM)
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desc_num = 0;
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priv->rx_currdescnum = desc_num;
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return 0;
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}
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static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
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{
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struct phy_device *phydev;
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int mask = 0xffffffff, ret;
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#ifdef CONFIG_PHY_ADDR
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mask = 1 << CONFIG_PHY_ADDR;
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#endif
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|
|
phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
|
|
if (!phydev)
|
|
return -ENODEV;
|
|
|
|
phy_connect_dev(phydev, dev);
|
|
|
|
phydev->supported &= PHY_GBIT_FEATURES;
|
|
if (priv->max_speed) {
|
|
ret = phy_set_supported(phydev, priv->max_speed);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
phydev->advertising = phydev->supported;
|
|
|
|
priv->phydev = phydev;
|
|
phy_config(phydev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifndef CONFIG_DM_ETH
|
|
static int dw_eth_init(struct eth_device *dev, bd_t *bis)
|
|
{
|
|
int ret;
|
|
|
|
ret = designware_eth_init(dev->priv, dev->enetaddr);
|
|
if (!ret)
|
|
ret = designware_eth_enable(dev->priv);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dw_eth_send(struct eth_device *dev, void *packet, int length)
|
|
{
|
|
return _dw_eth_send(dev->priv, packet, length);
|
|
}
|
|
|
|
static int dw_eth_recv(struct eth_device *dev)
|
|
{
|
|
uchar *packet;
|
|
int length;
|
|
|
|
length = _dw_eth_recv(dev->priv, &packet);
|
|
if (length == -EAGAIN)
|
|
return 0;
|
|
net_process_received_packet(packet, length);
|
|
|
|
_dw_free_pkt(dev->priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dw_eth_halt(struct eth_device *dev)
|
|
{
|
|
return _dw_eth_halt(dev->priv);
|
|
}
|
|
|
|
static int dw_write_hwaddr(struct eth_device *dev)
|
|
{
|
|
return _dw_write_hwaddr(dev->priv, dev->enetaddr);
|
|
}
|
|
|
|
int designware_initialize(ulong base_addr, u32 interface)
|
|
{
|
|
struct eth_device *dev;
|
|
struct dw_eth_dev *priv;
|
|
|
|
dev = (struct eth_device *) malloc(sizeof(struct eth_device));
|
|
if (!dev)
|
|
return -ENOMEM;
|
|
|
|
/*
|
|
* Since the priv structure contains the descriptors which need a strict
|
|
* buswidth alignment, memalign is used to allocate memory
|
|
*/
|
|
priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
|
|
sizeof(struct dw_eth_dev));
|
|
if (!priv) {
|
|
free(dev);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
|
|
printf("designware: buffers are outside DMA memory\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
memset(dev, 0, sizeof(struct eth_device));
|
|
memset(priv, 0, sizeof(struct dw_eth_dev));
|
|
|
|
sprintf(dev->name, "dwmac.%lx", base_addr);
|
|
dev->iobase = (int)base_addr;
|
|
dev->priv = priv;
|
|
|
|
priv->dev = dev;
|
|
priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
|
|
priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
|
|
DW_DMA_BASE_OFFSET);
|
|
|
|
dev->init = dw_eth_init;
|
|
dev->send = dw_eth_send;
|
|
dev->recv = dw_eth_recv;
|
|
dev->halt = dw_eth_halt;
|
|
dev->write_hwaddr = dw_write_hwaddr;
|
|
|
|
eth_register(dev);
|
|
|
|
priv->interface = interface;
|
|
|
|
dw_mdio_init(dev->name, priv->mac_regs_p);
|
|
priv->bus = miiphy_get_dev_by_name(dev->name);
|
|
|
|
return dw_phy_init(priv, dev);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_DM_ETH
|
|
static int designware_eth_start(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
struct dw_eth_dev *priv = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
ret = designware_eth_init(priv, pdata->enetaddr);
|
|
if (ret)
|
|
return ret;
|
|
ret = designware_eth_enable(priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int designware_eth_send(struct udevice *dev, void *packet, int length)
|
|
{
|
|
struct dw_eth_dev *priv = dev_get_priv(dev);
|
|
|
|
return _dw_eth_send(priv, packet, length);
|
|
}
|
|
|
|
int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
{
|
|
struct dw_eth_dev *priv = dev_get_priv(dev);
|
|
|
|
return _dw_eth_recv(priv, packetp);
|
|
}
|
|
|
|
int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
|
|
{
|
|
struct dw_eth_dev *priv = dev_get_priv(dev);
|
|
|
|
return _dw_free_pkt(priv);
|
|
}
|
|
|
|
void designware_eth_stop(struct udevice *dev)
|
|
{
|
|
struct dw_eth_dev *priv = dev_get_priv(dev);
|
|
|
|
return _dw_eth_halt(priv);
|
|
}
|
|
|
|
int designware_eth_write_hwaddr(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
struct dw_eth_dev *priv = dev_get_priv(dev);
|
|
|
|
return _dw_write_hwaddr(priv, pdata->enetaddr);
|
|
}
|
|
|
|
static int designware_eth_bind(struct udevice *dev)
|
|
{
|
|
#ifdef CONFIG_DM_PCI
|
|
static int num_cards;
|
|
char name[20];
|
|
|
|
/* Create a unique device name for PCI type devices */
|
|
if (device_is_on_pci_bus(dev)) {
|
|
sprintf(name, "eth_designware#%u", num_cards++);
|
|
device_set_name(dev, name);
|
|
}
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int designware_eth_probe(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
struct dw_eth_dev *priv = dev_get_priv(dev);
|
|
u32 iobase = pdata->iobase;
|
|
ulong ioaddr;
|
|
int ret;
|
|
#ifdef CONFIG_CLK
|
|
int i, err, clock_nb;
|
|
|
|
priv->clock_count = 0;
|
|
clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
|
|
if (clock_nb > 0) {
|
|
priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
|
|
GFP_KERNEL);
|
|
if (!priv->clocks)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < clock_nb; i++) {
|
|
err = clk_get_by_index(dev, i, &priv->clocks[i]);
|
|
if (err < 0)
|
|
break;
|
|
|
|
err = clk_enable(&priv->clocks[i]);
|
|
if (err && err != -ENOSYS && err != -ENOTSUPP) {
|
|
pr_err("failed to enable clock %d\n", i);
|
|
clk_free(&priv->clocks[i]);
|
|
goto clk_err;
|
|
}
|
|
priv->clock_count++;
|
|
}
|
|
} else if (clock_nb != -ENOENT) {
|
|
pr_err("failed to get clock phandle(%d)\n", clock_nb);
|
|
return clock_nb;
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_DM_REGULATOR)
|
|
struct udevice *phy_supply;
|
|
|
|
ret = device_get_supply_regulator(dev, "phy-supply",
|
|
&phy_supply);
|
|
if (ret) {
|
|
debug("%s: No phy supply\n", dev->name);
|
|
} else {
|
|
ret = regulator_set_enable(phy_supply, true);
|
|
if (ret) {
|
|
puts("Error enabling phy supply\n");
|
|
return ret;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_DM_PCI
|
|
/*
|
|
* If we are on PCI bus, either directly attached to a PCI root port,
|
|
* or via a PCI bridge, fill in platdata before we probe the hardware.
|
|
*/
|
|
if (device_is_on_pci_bus(dev)) {
|
|
dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
|
|
iobase &= PCI_BASE_ADDRESS_MEM_MASK;
|
|
iobase = dm_pci_mem_to_phys(dev, iobase);
|
|
|
|
pdata->iobase = iobase;
|
|
pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
|
|
}
|
|
#endif
|
|
|
|
debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
|
|
ioaddr = iobase;
|
|
priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
|
|
priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
|
|
priv->interface = pdata->phy_interface;
|
|
priv->max_speed = pdata->max_speed;
|
|
|
|
dw_mdio_init(dev->name, dev);
|
|
priv->bus = miiphy_get_dev_by_name(dev->name);
|
|
|
|
ret = dw_phy_init(priv, dev);
|
|
debug("%s, ret=%d\n", __func__, ret);
|
|
|
|
return ret;
|
|
|
|
#ifdef CONFIG_CLK
|
|
clk_err:
|
|
ret = clk_release_all(priv->clocks, priv->clock_count);
|
|
if (ret)
|
|
pr_err("failed to disable all clocks\n");
|
|
|
|
return err;
|
|
#endif
|
|
}
|
|
|
|
static int designware_eth_remove(struct udevice *dev)
|
|
{
|
|
struct dw_eth_dev *priv = dev_get_priv(dev);
|
|
|
|
free(priv->phydev);
|
|
mdio_unregister(priv->bus);
|
|
mdio_free(priv->bus);
|
|
|
|
#ifdef CONFIG_CLK
|
|
return clk_release_all(priv->clocks, priv->clock_count);
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|
|
|
|
const struct eth_ops designware_eth_ops = {
|
|
.start = designware_eth_start,
|
|
.send = designware_eth_send,
|
|
.recv = designware_eth_recv,
|
|
.free_pkt = designware_eth_free_pkt,
|
|
.stop = designware_eth_stop,
|
|
.write_hwaddr = designware_eth_write_hwaddr,
|
|
};
|
|
|
|
int designware_eth_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
|
|
#ifdef CONFIG_DM_GPIO
|
|
struct dw_eth_dev *priv = dev_get_priv(dev);
|
|
#endif
|
|
struct eth_pdata *pdata = &dw_pdata->eth_pdata;
|
|
const char *phy_mode;
|
|
#ifdef CONFIG_DM_GPIO
|
|
int reset_flags = GPIOD_IS_OUT;
|
|
#endif
|
|
int ret = 0;
|
|
|
|
pdata->iobase = dev_read_addr(dev);
|
|
pdata->phy_interface = -1;
|
|
phy_mode = dev_read_string(dev, "phy-mode");
|
|
if (phy_mode)
|
|
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
|
|
if (pdata->phy_interface == -1) {
|
|
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
|
|
return -EINVAL;
|
|
}
|
|
|
|
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
|
|
|
|
#ifdef CONFIG_DM_GPIO
|
|
if (dev_read_bool(dev, "snps,reset-active-low"))
|
|
reset_flags |= GPIOD_ACTIVE_LOW;
|
|
|
|
ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
|
|
&priv->reset_gpio, reset_flags);
|
|
if (ret == 0) {
|
|
ret = dev_read_u32_array(dev, "snps,reset-delays-us",
|
|
dw_pdata->reset_delays, 3);
|
|
} else if (ret == -ENOENT) {
|
|
ret = 0;
|
|
}
|
|
#endif
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct udevice_id designware_eth_ids[] = {
|
|
{ .compatible = "allwinner,sun7i-a20-gmac" },
|
|
{ .compatible = "altr,socfpga-stmmac" },
|
|
{ .compatible = "amlogic,meson6-dwmac" },
|
|
{ .compatible = "amlogic,meson-gx-dwmac" },
|
|
{ .compatible = "st,stm32-dwmac" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(eth_designware) = {
|
|
.name = "eth_designware",
|
|
.id = UCLASS_ETH,
|
|
.of_match = designware_eth_ids,
|
|
.ofdata_to_platdata = designware_eth_ofdata_to_platdata,
|
|
.bind = designware_eth_bind,
|
|
.probe = designware_eth_probe,
|
|
.remove = designware_eth_remove,
|
|
.ops = &designware_eth_ops,
|
|
.priv_auto_alloc_size = sizeof(struct dw_eth_dev),
|
|
.platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
|
};
|
|
|
|
static struct pci_device_id supported[] = {
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_PCI_DEVICE(eth_designware, supported);
|
|
#endif
|