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https://github.com/brain-hackers/u-boot-brain
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d26b40450b
This patch adds a DM based driver model for gpio controller present in FU540-C000 SoC on HiFive Unleashed A00 board. This SoC has one GPIO bank and 16 GPIO lines in total, out of which GPIO0 to GPIO9 and GPIO15 are routed to the J1 header on the board. This implementation is ported from linux based gpio driver submitted for review by Wesley W. Terpstra <wesley@sifive.com> and/or Atish Patra <atish.patra@wdc.com> (many thanks !!). The linux driver can be referred here [1] [1]: https://lkml.org/lkml/2018/10/9/1103 Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
36 lines
690 B
C
36 lines
690 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2019 SiFive, Inc.
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*/
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#ifndef _GPIO_SIFIVE_H
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#define _GPIO_SIFIVE_H
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#define GPIO_INPUT_VAL 0x00
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#define GPIO_INPUT_EN 0x04
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#define GPIO_OUTPUT_EN 0x08
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#define GPIO_OUTPUT_VAL 0x0C
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#define GPIO_RISE_IE 0x18
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#define GPIO_RISE_IP 0x1C
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#define GPIO_FALL_IE 0x20
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#define GPIO_FALL_IP 0x24
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#define GPIO_HIGH_IE 0x28
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#define GPIO_HIGH_IP 0x2C
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#define GPIO_LOW_IE 0x30
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#define GPIO_LOW_IP 0x34
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#define GPIO_OUTPUT_XOR 0x40
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#define NR_GPIOS 16
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enum gpio_state {
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LOW,
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HIGH
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};
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/* Details about a GPIO bank */
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struct sifive_gpio_platdata {
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void *base; /* address of registers in physical memory */
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};
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#endif /* _GPIO_SIFIVE_H */
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