mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
25ddd1fb0a
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
275 lines
8.9 KiB
C
275 lines
8.9 KiB
C
/*
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* Copyright (C) 2004 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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*
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* U-Boot configuration for Embedded Planet EP8248 boards.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_MPC8248
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#define CPU_ID_STR "MPC8248"
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#define CONFIG_EP8248 /* Embedded Planet EP8248 board */
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
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#define CONFIG_ENV_OVERWRITE
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/*
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* Select serial console configuration
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*
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* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*/
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#define CONFIG_CONS_ON_SMC /* Console is on SMC */
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#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
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#undef CONFIG_CONS_NONE /* It's not on external UART */
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#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
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#define CONFIG_SYS_BCSR 0xFA000000
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/* Pass open firmware flat device tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define OF_TBCLK (bd->bi_busfreq / 4)
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#define OF_STDOUT_PATH "/soc/cpm/serial <at> 11a80"
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/* Select ethernet configuration */
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#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
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#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
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#undef CONFIG_ETHER_NONE /* No external Ethernet */
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#define CONFIG_NET_MULTI
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#define CONFIG_SYS_CPMFCR_RAMTYPE 0
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#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
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#define CONFIG_HAS_ETH0
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#define CONFIG_ETHER_ON_FCC1 1
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/* - Rx clock is CLK10
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* - Tx clock is CLK11
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* - BDs/buffers on 60x bus
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* - Full duplex
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*/
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#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
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#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
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#define CONFIG_HAS_ETH1
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#define CONFIG_ETHER_ON_FCC2 1
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/* - Rx clock is CLK13
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* - Tx clock is CLK14
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* - BDs/buffers on 60x bus
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* - Full duplex
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*/
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#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
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#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
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#define CONFIG_MII /* MII PHY management */
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#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
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/*
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* GPIO pins used for bit-banged MII communications
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*/
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#define MDIO_PORT 0 /* Not used - implemented in BCSR */
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#define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
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#define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
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#define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
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#define MDIO(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
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else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
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#define MDC(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
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else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
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#define MIIDELAY udelay(1)
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#ifndef CONFIG_8260_CLKIN
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#define CONFIG_8260_CLKIN 66000000 /* in Hz */
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#endif
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#define CONFIG_BAUDRATE 38400
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ECHO
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IMMAP
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */
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#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
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#if defined(CONFIG_CMD_KGDB)
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#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
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#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
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#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
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#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
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#endif
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#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
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#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#define CONFIG_SYS_FLASH_BASE 0xFF800000
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
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#define CONFIG_SYS_DIRECT_FLASH_TFTP
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#if defined(CONFIG_CMD_JFFS2)
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#define CONFIG_SYS_JFFS2_FIRST_BANK 0
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#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
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#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0
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#define CONFIG_SYS_JFFS2_LAST_SECTOR 62
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#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
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#define CONFIG_SYS_JFFS_CUSTOM_PART
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#endif
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#if defined(CONFIG_CMD_I2C)
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#define CONFIG_HARD_I2C 1 /* To enable I2C support */
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#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
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#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
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#endif
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
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#define CONFIG_ENV_IS_IN_FLASH
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#endif /* CONFIG_ENV_IS_IN_FLASH */
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#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
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#define CONFIG_SYS_IMMR 0xF0000000
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/* Hard reset configuration word */
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#define CONFIG_SYS_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */
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/* No slaves */
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#define CONFIG_SYS_HRCW_SLAVE1 0
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#define CONFIG_SYS_HRCW_SLAVE2 0
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#define CONFIG_SYS_HRCW_SLAVE3 0
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#define CONFIG_SYS_HRCW_SLAVE4 0
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#define CONFIG_SYS_HRCW_SLAVE5 0
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#define CONFIG_SYS_HRCW_SLAVE6 0
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#define CONFIG_SYS_HRCW_SLAVE7 0
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#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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#define CONFIG_SYS_HID0_INIT 0
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#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
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#define CONFIG_SYS_HID2 0
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#define CONFIG_SYS_SIUMCR 0x01240200
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#define CONFIG_SYS_SYPCR 0xFFFF0683
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#define CONFIG_SYS_BCR 0x00000000
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#define CONFIG_SYS_SCCR SCCR_DFBRG01
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#define CONFIG_SYS_RMR RMR_CSRE
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#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
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#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
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#define CONFIG_SYS_RCCR 0
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#define CONFIG_SYS_MPTPR 0x1300
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#define CONFIG_SYS_PSDMR 0x82672522
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#define CONFIG_SYS_PSRT 0x4B
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00001841)
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#define CONFIG_SYS_SDRAM_OR 0xFF0030C0
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
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#define CONFIG_SYS_OR0_PRELIM 0xFF8008C2
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#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
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#define CONFIG_SYS_OR2_PRELIM 0xFFF00864
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#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
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#endif /* __CONFIG_H */
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