mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
25ddd1fb0a
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
475 lines
16 KiB
C
475 lines
16 KiB
C
/*
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* (C) Copyright 2002 ELTEC Elektronik AG
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* Frank Gottschling <fgottschling@eltec.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define GTREGREAD(x) 0xffffffff /* needed for debug */
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000
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/* these hardware addresses are pretty bogus, please change them to
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suit your needs */
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/* first ethernet */
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#define CONFIG_ETHADDR 00:00:5b:ee:de:ad
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#define CONFIG_IPADDR 192.168.0.105
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#define CONFIG_SERVERIP 192.168.0.100
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#define CONFIG_BAB7xx 1 /* this is an BAB740/BAB750 board */
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#define CONFIG_BAUDRATE 9600 /* console baudrate */
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#undef CONFIG_WATCHDOG
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"bootp 1000000; " \
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"setenv bootargs root=ramfs console=ttyS00,9600 " \
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"ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \
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"${netmask}:${hostname}:eth0:none; " \
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"bootm"
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#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_SCSI
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_FDC
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#define CONFIG_CMD_ELF
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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/*
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* choose between COM1 and COM2 as serial console
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*/
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#define CONFIG_CONS_INDEX 1
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
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#define CONFIG_SYS_HZ 1000 /* dec. freq: 1 ms ticks */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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#define CONFIG_SYS_BOARD_ASM_INIT
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#define CONFIG_MISC_INIT_R
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/*
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* Choose the address mapping scheme for the MPC106 mem controller.
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* Default is mapping B (CHRP), set this define to choose mapping A (PReP).
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*/
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#define CONFIG_SYS_ADDRESS_MAP_A
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#ifdef CONFIG_SYS_ADDRESS_MAP_A
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#define CONFIG_SYS_PCI_MEMORY_BUS 0x80000000
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#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
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#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
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#define CONFIG_SYS_PCI_MEM_BUS 0x00000000
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#define CONFIG_SYS_PCI_MEM_PHYS 0xc0000000
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#define CONFIG_SYS_PCI_MEM_SIZE 0x3f000000
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#define CONFIG_SYS_ISA_MEM_BUS 0
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#define CONFIG_SYS_ISA_MEM_PHYS 0
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#define CONFIG_SYS_ISA_MEM_SIZE 0
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#define CONFIG_SYS_PCI_IO_BUS 0x1000
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#define CONFIG_SYS_PCI_IO_PHYS 0x81000000
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#define CONFIG_SYS_PCI_IO_SIZE 0x01000000-CONFIG_SYS_PCI_IO_BUS
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#define CONFIG_SYS_ISA_IO_BUS 0x00000000
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#define CONFIG_SYS_ISA_IO_PHYS 0x80000000
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#define CONFIG_SYS_ISA_IO_SIZE 0x00800000
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#else
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#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
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#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
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#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000
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#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
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#define CONFIG_SYS_PCI_MEM_SIZE 0x7d000000
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#define CONFIG_SYS_ISA_MEM_BUS 0x00000000
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#define CONFIG_SYS_ISA_MEM_PHYS 0xfd000000
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#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000
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#define CONFIG_SYS_PCI_IO_BUS 0x00800000
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#define CONFIG_SYS_PCI_IO_PHYS 0xfe800000
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#define CONFIG_SYS_PCI_IO_SIZE 0x00400000
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#define CONFIG_SYS_ISA_IO_BUS 0x00000000
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#define CONFIG_SYS_ISA_IO_PHYS 0xfe000000
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#define CONFIG_SYS_ISA_IO_SIZE 0x00800000
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#endif /*CONFIG_SYS_ADDRESS_MAP_A */
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#define CONFIG_SYS_60X_PCI_MEM_OFFSET 0x00000000
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/* driver defines FDC,IDE,... */
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#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
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#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS
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#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS
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/*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0xfff00000
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/*
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* Definitions for initial stack pointer and data area
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*
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* Flash mapping/organization on the MPC10x.
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*/
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#define FLASH_BASE0_PRELIM 0xff800000
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#define FLASH_BASE1_PRELIM 0xffc00000
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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/*
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* JFFS2 partitions
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*
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*/
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/* No command line, one static partition */
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#undef CONFIG_CMD_MTDPARTS
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#define CONFIG_JFFS2_DEV "nor"
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#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
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#define CONFIG_JFFS2_PART_OFFSET 0x00000000
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/* mtdparts command line support
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*
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* Note: fake mtd_id used, no linux mtd map file
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*/
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/*
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#define CONFIG_CMD_MTDPARTS
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#define MTDIDS_DEFAULT "nor0=bab7xx-0"
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#define MTDPARTS_DEFAULT "mtdparts=bab7xx-0:-(jffs2)"
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */
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#undef CONFIG_SYS_MEMTEST
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
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#define CONFIG_SYS_NVRAM_SIZE 0x1ff0 /* NVRAM size (8kB), we must protect the clock data (16 bytes) */
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#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */
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/*
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* We store the environment and an image of revision eeprom in the upper part of the NVRAM. Thus,
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* user applications can use the remaining space for other purposes.
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*/
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#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_SIZE +0x10 -0x800)
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#define CONFIG_SYS_NV_SROM_COPY_ADDR (CONFIG_SYS_NVRAM_SIZE +0x10 -0x400)
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#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE /* This board needs a special routine to access the NVRAM */
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#define CONFIG_SYS_SROM_SIZE 0x100 /* shadow of revision info is in nvram */
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/*
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* Serial devices
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*/
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK 1843200
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
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/*
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* PCI stuff
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*/
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_SYS_EARLY_PCI_INIT
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#define CONFIG_PCI_PNP /* pci plug-and-play */
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#define CONFIG_PCI_HOST PCI_HOST_AUTO
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#undef CONFIG_PCI_SCAN_SHOW
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/*
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* Video console (graphic: SMI LynxEM, keyboard: i8042)
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*/
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#define CONFIG_VIDEO
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_SMI_LYNXEM
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#define CONFIG_I8042_KBD
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_CONSOLE_TIME
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#define CONFIG_CONSOLE_EXTRA_INFO
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#define CONFIG_CONSOLE_CURSOR
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#define CONFIG_SYS_CONSOLE_BLINK_COUNT 30000 /* approx. 2 HZ */
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/*
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* IDE/SCSI globals
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*/
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#ifndef __ASSEMBLY__
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extern unsigned int eltec_board;
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extern unsigned int ata_reset_time;
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extern unsigned int scsi_reset_time;
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extern unsigned short scsi_dev_id;
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extern unsigned int scsi_max_scsi_id;
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extern unsigned char scsi_sym53c8xx_ccf;
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#endif
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/*
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* ATAPI Support (experimental)
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*/
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#define CONFIG_ATAPI
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#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */
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#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
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#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_60X_PCI_IO_OFFSET /* base address */
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1F0 /* default ide0 offste */
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#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 /* default ide1 offset */
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#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
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#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
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#define ATA_RESET_TIME (ata_reset_time)
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#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
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#undef CONFIG_IDE_LED /* no led for ide supported */
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/*
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* SCSI support (experimental) only SYM53C8xx supported
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*/
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#define CONFIG_SCSI_SYM53C8XX
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#define CONFIG_SCSI_DEV_ID (scsi_dev_id) /* 875 or 860 */
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#define CONFIG_SYS_SCSI_SYM53C8XX_CCF (scsi_sym53c8xx_ccf) /* value for none 40 mhz clocks */
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#define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */
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#define CONFIG_SYS_SCSI_MAX_SCSI_ID (scsi_max_scsi_id) /* max SCSI ID (0-6) */
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#define CONFIG_SYS_SCSI_MAX_DEVICE (15 * CONFIG_SYS_SCSI_MAX_LUN) /* max. Target devices */
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#define CONFIG_SYS_SCSI_SPIN_UP_TIME (scsi_reset_time)
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/*
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* Partion suppport
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*/
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#define CONFIG_DOS_PARTITION
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#define CONFIG_MAC_PARTITION
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#define CONFIG_ISO_PARTITION
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/*
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* Winbond Configuration
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*/
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#define CONFIG_WINBOND_83C553 1 /* has a winbond bridge */
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#define CONFIG_SYS_USE_WINBOND_IDE 0 /* use winbond 83c553 internal ide */
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#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /* pci-isa bridge config addr */
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#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /* ide config addr */
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/*
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* NS87308 Configuration
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*/
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#define CONFIG_NS87308 /* Nat Semi super-io cntr on ISA bus */
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#define CONFIG_SYS_NS87308_BADDR_10 1
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#define CONFIG_SYS_NS87308_DEVS (CONFIG_SYS_NS87308_UART1 | \
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CONFIG_SYS_NS87308_UART2 | \
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CONFIG_SYS_NS87308_KBC1 | \
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CONFIG_SYS_NS87308_MOUSE | \
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CONFIG_SYS_NS87308_FDC | \
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CONFIG_SYS_NS87308_RARP | \
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CONFIG_SYS_NS87308_GPIO | \
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CONFIG_SYS_NS87308_POWRMAN | \
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CONFIG_SYS_NS87308_RTC_APC )
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#define CONFIG_SYS_NS87308_PS2MOD
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#define CONFIG_SYS_NS87308_GPIO_BASE 0x0220
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#define CONFIG_SYS_NS87308_PWMAN_BASE 0x0460
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#define CONFIG_SYS_NS87308_PMC2 0x00 /* SuperI/O clock source is 24MHz via X1 */
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/*
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* set up the NVRAM access registers
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* NVRAM's controlled by the configurable CS line from the 87308
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*/
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#define CONFIG_SYS_NS87308_CS0_BASE 0x0076
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#define CONFIG_SYS_NS87308_CS0_CONF 0x40
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#define CONFIG_SYS_NS87308_CS1_BASE 0x0070
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#define CONFIG_SYS_NS87308_CS1_CONF 0x1C
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#define CONFIG_SYS_NS87308_CS2_BASE 0x0071
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#define CONFIG_SYS_NS87308_CS2_CONF 0x1C
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#define CONFIG_RTC_MK48T59
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/*
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* Initial BATs
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*/
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#if 1
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#define CONFIG_SYS_IBAT0L 0
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#define CONFIG_SYS_IBAT0U 0
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
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#define CONFIG_SYS_IBAT1L 0
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#define CONFIG_SYS_IBAT1U 0
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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#define CONFIG_SYS_IBAT2L 0
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#define CONFIG_SYS_IBAT2U 0
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#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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#define CONFIG_SYS_IBAT3L 0
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#define CONFIG_SYS_IBAT3U 0
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#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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#else
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/* SDRAM */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_RW)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
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/* address range for flashes */
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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/* ISA IO space */
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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/* ISA memory space */
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#define CONFIG_SYS_IBAT3L (CONFIG_SYS_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT3U (CONFIG_SYS_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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#endif
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/*
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* Speed settings are board specific
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*/
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#ifndef __ASSEMBLY__
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extern unsigned long bab7xx_get_bus_freq (void);
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extern unsigned long bab7xx_get_gclk_freq (void);
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#endif
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#define CONFIG_SYS_BUS_CLK bab7xx_get_bus_freq()
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#define CONFIG_SYS_CPU_CLK bab7xx_get_gclk_freq()
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* L2 Cache Configuration is board specific for BAB740/BAB750
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* Init values read from revision srom.
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*/
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#undef CONFIG_SYS_L2
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#define L2_INIT (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
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L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
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#define L2_ENABLE (L2_INIT | L2CR_L2E)
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#define CONFIG_SYS_L2_BAB7xx
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#define CONFIG_NET_MULTI /* Multi ethernet cards support */
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#define CONFIG_TULIP
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#define CONFIG_TULIP_SELECT_MEDIA
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#endif /* __CONFIG_H */
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