mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
0a9ef45158
This converts the following to Kconfig:
CONFIG_NAND_MXC
CONFIG_NAND_OMAP_GPMC
CONFIG_NAND_OMAP_GPMC_PREFETCH
CONFIG_NAND_OMAP_ELM
CONFIG_SPL_NAND_AM33XX_BCH
CONFIG_SPL_NAND_SIMPLE
CONFIG_SYS_NAND_BUSWIDTH_16BIT
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
[trini: Finish migration of CONFIG_SPL_NAND_SIMPLE, fix some build issues,
add CONFIG_NAND_MXC so we can do CONFIG_SYS_NAND_BUSWIDTH_16BIT]
Signed-off-by: Tom Rini <trini@konsulko.com>
111 lines
3.0 KiB
C
111 lines
3.0 KiB
C
/*
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* (C) Copyright 2013
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* Texas Instruments Incorporated.
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* Sricharan R <r.sricharan@ti.com>
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*
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* Derived from OMAP4 done by:
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* Aneesh V <aneesh@ti.com>
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*
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* TI OMAP5 AND DRA7XX common configuration settings
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* For more details, please see the technical documents listed at
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* http://www.ti.com/product/omap5432
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*/
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#ifndef __CONFIG_TI_OMAP5_COMMON_H
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#define __CONFIG_TI_OMAP5_COMMON_H
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/* Use General purpose timer 1 */
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#define CONFIG_SYS_TIMERBASE GPT2_BASE
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/*
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* For the DDR timing information we can either dynamically determine
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* the timings to use or use pre-determined timings (based on using the
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* dynamic method. Default to the static timing infomation.
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*/
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#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
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#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
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#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
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#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
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#endif
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#define CONFIG_PALMAS_POWER
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#include <asm/arch/cpu.h>
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#include <asm/arch/omap.h>
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#include <configs/ti_armv7_omap.h>
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/*
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* Hardware drivers
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*/
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#define CONFIG_SYS_NS16550_CLK 48000000
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#if !defined(CONFIG_DM_SERIAL)
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#endif
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/*
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* Environment setup
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*/
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#ifndef DFUARGS
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#define DFUARGS
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#endif
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#include <environment/ti/boot.h>
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#include <environment/ti/mmc.h>
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#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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#define CONFIG_EXTRA_ENV_SETTINGS \
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DEFAULT_LINUX_BOOT_ENV \
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DEFAULT_MMC_TI_ARGS \
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DEFAULT_FIT_TI_ARGS \
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DEFAULT_COMMON_BOOT_TI_ARGS \
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DEFAULT_FDT_TI_ARGS \
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DFUARGS \
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NETARGS \
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/*
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* SPL related defines. The Public RAM memory map the ROM defines the
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* area between 0x40300000 and 0x4031E000 as a download area for OMAP5.
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* On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000.
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* We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
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* print some information.
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*/
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#ifdef CONFIG_TI_SECURE_DEVICE
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/*
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* For memory booting on HS parts, the first 4KB of the internal RAM is
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* reserved for secure world use and the flash loader image is
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* preceded by a secure certificate. The SPL will therefore run in internal
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* RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)).
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*/
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#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000
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#define CONFIG_SPL_TEXT_BASE 0x40301350
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/* If no specific start address is specified then the secure EMIF
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* region will be placed at the end of the DDR space. In order to prevent
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* the main u-boot relocation from clobbering that memory and causing a
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* firewall violation, we tell u-boot that memory is protected RAM (PRAM)
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*/
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#if (CONFIG_TI_SECURE_EMIF_REGION_START == 0)
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#define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10
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#endif
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#else
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/*
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* For all booting on GP parts, the flash loader image is
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* downloaded into internal RAM at address 0x40300000.
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*/
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#define CONFIG_SPL_TEXT_BASE 0x40300000
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#endif
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#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
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(128 << 20))
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#ifdef CONFIG_SPL_BUILD
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#undef CONFIG_TIMER
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#endif
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#endif /* __CONFIG_TI_OMAP5_COMMON_H */
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