Mugunthan V N 7fb825f5b1 omap5/dra7: i2c: correct register offset for sync register ... The register offset of i2c_sysc offset is not correct as per omap5[1]/dra7[2] TRM, correct the offsets as per the documentation. [1] - http://www.ti.com/lit/pdf/swpu249 [2] - http://www.ti.com/lit/pdf/spruhz6 Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>		2016-07-26 08:39:23 +02:00
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clock.h	ARM: DRA7: Add macros for voltage values for all OPPs	2016-06-02 21:42:17 -04:00
cpu.h	ARM: omap5: add platform specific ethernet phy modes configurations	2016-05-24 11:42:02 -05:00
dra7xx_iodelay.h	ARM: OMAP5/DRA7: Expose do_set_iodelay	2016-03-27 09:12:15 -04:00
ehci.h
gpio.h
hardware.h	ARM: dra7xx_evm: Enable EDMA3 in SPL to support DMA on qspi	2015-08-17 23:29:15 +05:30
i2c.h	omap5/dra7: i2c: correct register offset for sync register	2016-07-26 08:39:23 +02:00
mem.h
mmc_host_def.h
mux_dra7xx.h	ARM: DRA7: Add support for manual mode configuration	2015-06-12 13:02:05 -04:00
mux_omap5.h
omap.h	ARM: DRA7: Add ABB setup for all domains	2016-04-25 15:10:41 -04:00
sata.h
spl.h	omap: SPL boot devices cleanup and completion	2015-07-27 15:02:04 -04:00
sys_proto.h	arm: omap: Introduce vcores_init function	2016-06-02 21:42:18 -04:00