mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
207 lines
5.4 KiB
C
207 lines
5.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2012 Calxeda, Inc.
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*/
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#include <common.h>
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#include <ahci.h>
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#include <asm/io.h>
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#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
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#define CPHY_ADDR(base, dev, addr) ((base) | (((addr) & 0x1ff) << 2))
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#define CPHY_BASE 0xfff58000
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#define CPHY_WIDTH 0x1000
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#define CPHY_DTE_XS 5
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#define CPHY_MII 31
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#define SERDES_CR_CTL 0x80a0
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#define SERDES_CR_ADDR 0x80a1
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#define SERDES_CR_DATA 0x80a2
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#define CR_BUSY 0x0001
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#define CR_START 0x0001
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#define CR_WR_RDN 0x0002
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#define CPHY_TX_INPUT_STS 0x2001
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#define CPHY_RX_INPUT_STS 0x2002
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#define CPHY_SATA_TX_OVERRIDE_BIT 0x8000
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#define CPHY_SATA_RX_OVERRIDE_BIT 0x4000
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#define CPHY_TX_INPUT_OVERRIDE 0x2004
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#define CPHY_RX_INPUT_OVERRIDE 0x2005
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#define SPHY_LANE 0x100
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#define SPHY_HALF_RATE 0x0001
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#define CPHY_SATA_DPLL_MODE 0x0700
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#define CPHY_SATA_DPLL_SHIFT 8
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#define CPHY_SATA_TX_ATTEN 0x1c00
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#define CPHY_SATA_TX_ATTEN_SHIFT 10
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#define HB_SREG_SATA_ATTEN 0xfff3cf24
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#define SATA_PORT_BASE 0xffe08000
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#define SATA_VERSIONR 0xf8
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#define SATA_HB_VERSION 0x3332302a
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static u32 __combo_phy_reg_read(u8 phy, u8 dev, u32 addr)
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{
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u32 data;
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writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
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data = readl(CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
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return data;
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}
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static void __combo_phy_reg_write(u8 phy, u8 dev, u32 addr, u32 data)
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{
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writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
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writel(data, CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
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}
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static u32 combo_phy_read(u8 phy, u32 addr)
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{
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u8 dev = CPHY_DTE_XS;
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if (phy == 5)
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dev = CPHY_MII;
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while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
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udelay(5);
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__combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
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__combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_START);
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while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
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udelay(5);
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return __combo_phy_reg_read(phy, dev, SERDES_CR_DATA);
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}
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static void combo_phy_write(u8 phy, u32 addr, u32 data)
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{
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u8 dev = CPHY_DTE_XS;
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if (phy == 5)
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dev = CPHY_MII;
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while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
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udelay(5);
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__combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
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__combo_phy_reg_write(phy, dev, SERDES_CR_DATA, data);
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__combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_WR_RDN | CR_START);
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}
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static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val)
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{
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u32 tmp;
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tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
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tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
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combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
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tmp |= CPHY_SATA_RX_OVERRIDE_BIT;
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combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
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tmp &= ~CPHY_SATA_DPLL_MODE;
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tmp |= (val << CPHY_SATA_DPLL_SHIFT) & CPHY_SATA_DPLL_MODE;
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combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
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}
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static void cphy_tx_attenuation_override(u8 phy, u8 lane)
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{
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u32 val;
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u32 tmp;
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u8 shift;
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shift = ((phy == 5) ? 4 : lane) * 4;
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val = (readl(HB_SREG_SATA_ATTEN) >> shift) & 0xf;
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if (val & 0x8)
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return;
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tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE);
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tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
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combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
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tmp |= CPHY_SATA_TX_OVERRIDE_BIT;
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combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
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tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN;
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combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
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}
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static void cphy_disable_port_overrides(u8 port)
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{
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u32 tmp;
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u8 lane = 0, phy = 0;
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if (port == 0)
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phy = 5;
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else if (port < 5)
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lane = port - 1;
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else
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return;
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tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
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tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
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combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
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tmp = combo_phy_read(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE);
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tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
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combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
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}
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void cphy_disable_overrides(void)
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{
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int i;
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u32 port_map;
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port_map = readl(0xffe08000 + HOST_PORTS_IMPL);
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for (i = 0; i < 5; i++) {
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if (port_map & (1 << i))
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cphy_disable_port_overrides(i);
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}
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}
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static void cphy_override_lane(u8 port)
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{
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u32 tmp, k = 0;
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u8 lane = 0, phy = 0;
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if (port == 0)
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phy = 5;
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else if (port < 5)
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lane = port - 1;
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else
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return;
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do {
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tmp = combo_phy_read(0, CPHY_RX_INPUT_STS +
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lane * SPHY_LANE);
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} while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
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cphy_spread_spectrum_override(phy, lane, 3);
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cphy_tx_attenuation_override(phy, lane);
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}
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#define WAIT_MS_LINKUP 4
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int ahci_link_up(struct ahci_uc_priv *probe_ent, int port)
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{
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u32 tmp;
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int j = 0;
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u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
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u32 is_highbank = readl(SATA_PORT_BASE + SATA_VERSIONR) ==
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SATA_HB_VERSION ? 1 : 0;
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/* Bring up SATA link.
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* SATA link bringup time is usually less than 1 ms; only very
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* rarely has it taken between 1-2 ms. Never seen it above 2 ms.
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*/
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while (j < WAIT_MS_LINKUP) {
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if (is_highbank && (j == 0)) {
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cphy_disable_port_overrides(port);
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writel(0x301, port_mmio + PORT_SCR_CTL);
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udelay(1000);
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writel(0x300, port_mmio + PORT_SCR_CTL);
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udelay(1000);
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cphy_override_lane(port);
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}
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tmp = readl(port_mmio + PORT_SCR_STAT);
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if ((tmp & 0xf) == 0x3)
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return 0;
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udelay(1000);
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j++;
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if ((j == WAIT_MS_LINKUP) && (tmp & 0xf))
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j = 0; /* retry phy reset */
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}
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return 1;
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}
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