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https://github.com/brain-hackers/u-boot-brain
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5f24680867
Rockchip SoCs have internal sram for bootrom data area and for sdram init program space. Introduce the base address in case we need to use it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
60 lines
1.4 KiB
C
60 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*/
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#ifndef __CONFIG_RK3128_COMMON_H
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#define __CONFIG_RK3128_COMMON_H
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#include "rockchip-common.h"
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_MALLOC_LEN (32 << 20)
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0
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#define COUNTER_FREQUENCY 24000000
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#define CONFIG_SYS_ARCH_TIMER
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#define CONFIG_SYS_HZ_CLOCK 24000000
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#define CONFIG_IRAM_BASE 0x10080000
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#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
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#define CONFIG_SYS_LOAD_ADDR 0x60800800
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
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/* RAW SD card / eMMC locations. */
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#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SYS_SDRAM_BASE 0x60000000
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#define SDRAM_MAX_SIZE 0x80000000
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
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#ifndef CONFIG_SPL_BUILD
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/* usb mass storage */
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#define ENV_MEM_LAYOUT_SETTINGS \
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"scriptaddr=0x60500000\0" \
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"pxefile_addr_r=0x60600000\0" \
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"fdt_addr_r=0x61f00000\0" \
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"kernel_addr_r=0x62000000\0" \
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"ramdisk_addr_r=0x64000000\0"
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#include <config_distro_bootcmd.h>
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#define CONFIG_EXTRA_ENV_SETTINGS \
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ENV_MEM_LAYOUT_SETTINGS \
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"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"partitions=" PARTS_DEFAULT \
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BOOTENV
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#endif
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#endif
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