mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 08:58:52 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
312 lines
6.8 KiB
C
312 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
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*
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* Copyright 2007 Embedded Specialties, Inc.
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*
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* Copyright 2004, 2007 Freescale Semiconductor.
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/fsl_serdes.h>
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#include <spd_sdram.h>
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#include <netdev.h>
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#include <tsec.h>
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#include <miiphy.h>
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#include <linux/libfdt.h>
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#include <fdt_support.h>
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void local_bus_init(void);
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int board_early_init_f (void)
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{
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return 0;
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}
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int checkboard (void)
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{
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volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
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volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
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printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
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in_8(rev) >> 4);
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/*
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* Initialize local bus.
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*/
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local_bus_init ();
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out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
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out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
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return 0;
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}
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/*
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* Initialize Local Bus
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*/
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void
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local_bus_init(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
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uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
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sys_info_t sysinfo;
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get_sys_info(&sysinfo);
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lbc_mhz = sysinfo.freq_localbus / 1000000;
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clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;
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debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
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out_be32(&gur->lbiuiplldcr1, 0x00078080);
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if (clkdiv == 16) {
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out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
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} else if (clkdiv == 8) {
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out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
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} else if (clkdiv == 4) {
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out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
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}
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/*
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* Local Bus Clock > 83.3 MHz. According to timing
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* specifications set LCRR[EADC] to 2 delay cycles.
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*/
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if (lbc_mhz > 83) {
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lcrr &= ~LCRR_EADC;
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lcrr |= LCRR_EADC_2;
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}
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/*
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* According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
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* disable PLL bypass for Local Bus Clock > 83 MHz.
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*/
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if (lbc_mhz >= 66)
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lcrr &= (~LCRR_DBYP); /* DLL Enabled */
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else
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lcrr |= LCRR_DBYP; /* DLL Bypass */
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out_be32(&lbc->lcrr, lcrr);
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asm("sync;isync;msync");
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/*
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* According to MPC8548ERMAD Rev.1.3 read back LCRR
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* and terminate with isync
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*/
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lcrr = in_be32(&lbc->lcrr);
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asm ("isync;");
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/* let DLL stabilize */
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udelay(500);
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out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
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out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
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}
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/*
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* Initialize SDRAM memory on the Local Bus.
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*/
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void lbc_sdram_init(void)
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{
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#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
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uint idx;
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const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
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volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
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uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
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uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
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puts(" SDRAM: ");
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print_size(size, "\n");
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/*
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* Setup SDRAM Base and Option Registers
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*/
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set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
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set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
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set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
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set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
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out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
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asm("msync");
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out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
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out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
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asm("msync");
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/*
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* Issue PRECHARGE ALL command.
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*/
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out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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*sdram_addr2 = 0xff;
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ppcDcbf((unsigned long) sdram_addr2);
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udelay(100);
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/*
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* Issue 8 AUTO REFRESH commands.
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*/
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for (idx = 0; idx < 8; idx++) {
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out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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*sdram_addr2 = 0xff;
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ppcDcbf((unsigned long) sdram_addr2);
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udelay(100);
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}
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/*
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* Issue 8 MODE-set command.
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*/
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out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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*sdram_addr2 = 0xff;
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ppcDcbf((unsigned long) sdram_addr2);
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udelay(100);
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/*
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* Issue RFEN command.
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*/
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out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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*sdram_addr2 = 0xff;
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ppcDcbf((unsigned long) sdram_addr2);
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udelay(200); /* Overkill. Must wait > 200 bus cycles */
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#endif /* enable SDRAM init */
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}
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#if defined(CONFIG_SYS_DRAM_TEST)
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int
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testdram(void)
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{
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uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
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uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
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uint *p;
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printf("Testing DRAM from 0x%08x to 0x%08x\n",
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CONFIG_SYS_MEMTEST_START,
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CONFIG_SYS_MEMTEST_END);
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printf("DRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("DRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("DRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("DRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("DRAM test passed.\n");
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return 0;
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}
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#endif
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#ifdef CONFIG_PCI1
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static struct pci_controller pci1_hose;
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#endif /* CONFIG_PCI1 */
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#ifdef CONFIG_PCI
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void
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pci_init_board(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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int first_free_busno = 0;
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#ifdef CONFIG_PCI1
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struct fsl_pci_info pci_info;
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u32 devdisr = in_be32(&gur->devdisr);
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u32 pordevsr = in_be32(&gur->pordevsr);
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u32 porpllsr = in_be32(&gur->porpllsr);
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
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uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
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uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
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uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
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printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
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(pci_32) ? 32 : 64,
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(pci_speed == 33000000) ? "33" :
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(pci_speed == 66000000) ? "66" : "unknown",
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pci_clk_sel ? "sync" : "async",
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pci_arb ? "arbiter" : "external-arbiter");
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SET_STD_PCI_INFO(pci_info, 1);
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set_next_law(pci_info.mem_phys,
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law_size_bits(pci_info.mem_size), pci_info.law);
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set_next_law(pci_info.io_phys,
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law_size_bits(pci_info.io_size), pci_info.law);
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first_free_busno = fsl_pci_init_port(&pci_info,
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&pci1_hose, first_free_busno);
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} else {
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printf("PCI: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
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#endif
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
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fsl_pcie_init_board(first_free_busno);
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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tsec_standard_init(bis);
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pci_eth_init(bis);
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return 0; /* otherwise cpu_eth_init gets run */
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}
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int last_stage_init(void)
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{
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return 0;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_FSL_PCI_INIT
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FT_FSL_PCI_SETUP;
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#endif
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return 0;
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}
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#endif
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