mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-21 01:18:52 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
449 lines
9.0 KiB
ArmAsm
449 lines
9.0 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2011, 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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* Copyright (C) 2011, 2012 Renesas Solutions Corp.
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*/
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#include <config.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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#include <asm/processor.h>
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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/* WDT */
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write32 WDTCSR_A, WDTCSR_D
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/* MMU */
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write32 MMUCR_A, MMUCR_D
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write32 FRQCR2_A, FRQCR2_D
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write32 FRQCR0_A, FRQCR0_D
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write32 CS0CTRL_A, CS0CTRL_D
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write32 CS1CTRL_A, CS1CTRL_D
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write32 CS0CTRL2_A, CS0CTRL2_D
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write32 CSPWCR0_A, CSPWCR0_D
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write32 CSPWCR1_A, CSPWCR1_D
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write32 CS1GDST_A, CS1GDST_D
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# clock mode check
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mov.l MODEMR, r1
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mov.l @r1, r0
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and #6, r0 /* Check 1 and 2 bit.*/
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cmp/eq #2, r0 /* 0x02 is 533Mhz mode */
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bt init_lbsc_533
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init_lbsc_400:
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write32 CSWCR0_A, CSWCR0_D_400
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write32 CSWCR1_A, CSWCR1_D
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bra init_dbsc3_400_pad
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nop
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.align 2
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MODEMR: .long 0xFFCC0020
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WDTCSR_A: .long 0xFFCC0004
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WDTCSR_D: .long 0xA5000000
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MMUCR_A: .long 0xFF000010
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MMUCR_D: .long 0x00000004
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FRQCR2_A: .long 0xFFC80008
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FRQCR2_D: .long 0x00000000
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FRQCR0_A: .long 0xFFC80000
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FRQCR0_D: .long 0xCF000001
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CS0CTRL_A: .long 0xFF800200
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CS0CTRL_D: .long 0x00000020
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CS1CTRL_A: .long 0xFF800204
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CS1CTRL_D: .long 0x00000020
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CS0CTRL2_A: .long 0xFF800220
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CS0CTRL2_D: .long 0x00004000
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CSPWCR0_A: .long 0xFF800280
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CSPWCR0_D: .long 0x00000000
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CSPWCR1_A: .long 0xFF800284
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CSPWCR1_D: .long 0x00000000
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CS1GDST_A: .long 0xFF8002C0
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CS1GDST_D: .long 0x00000011
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init_lbsc_533:
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write32 CSWCR0_A, CSWCR0_D_533
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write32 CSWCR1_A, CSWCR1_D
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bra init_dbsc3_533_pad
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nop
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.align 2
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CSWCR0_A: .long 0xFF800230
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CSWCR0_D_533: .long 0x01120104
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CSWCR0_D_400: .long 0x02120114
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CSWCR1_A: .long 0xFF800234
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CSWCR1_D: .long 0x077F077F
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init_dbsc3_400_pad:
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write32 DBPDCNT3_A, DBPDCNT3_D
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wait_timer WAIT_200US_400
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write32 DBPDCNT0_A, DBPDCNT0_D_400
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write32 DBPDCNT3_A, DBPDCNT3_D0
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write32 DBPDCNT1_A, DBPDCNT1_D
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write32 DBPDCNT3_A, DBPDCNT3_D1
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wait_timer WAIT_32MCLK
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write32 DBPDCNT3_A, DBPDCNT3_D2
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wait_timer WAIT_100US_400
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write32 DBPDCNT3_A, DBPDCNT3_D3
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wait_timer WAIT_16MCLK
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write32 DBPDCNT3_A, DBPDCNT3_D4
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wait_timer WAIT_200US_400
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write32 DBPDCNT3_A, DBPDCNT3_D5
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wait_timer WAIT_1MCLK
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write32 DBPDCNT3_A, DBPDCNT3_D6
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wait_timer WAIT_10KMCLK
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bra init_dbsc3_ctrl_400
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nop
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.align 2
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init_dbsc3_533_pad:
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write32 DBPDCNT3_A, DBPDCNT3_D
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wait_timer WAIT_200US_533
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write32 DBPDCNT0_A, DBPDCNT0_D_533
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write32 DBPDCNT3_A, DBPDCNT3_D0
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write32 DBPDCNT1_A, DBPDCNT1_D
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write32 DBPDCNT3_A, DBPDCNT3_D1
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wait_timer WAIT_32MCLK
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write32 DBPDCNT3_A, DBPDCNT3_D2
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wait_timer WAIT_100US_533
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write32 DBPDCNT3_A, DBPDCNT3_D3
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wait_timer WAIT_16MCLK
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write32 DBPDCNT3_A, DBPDCNT3_D4
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wait_timer WAIT_200US_533
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write32 DBPDCNT3_A, DBPDCNT3_D5
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wait_timer WAIT_1MCLK
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write32 DBPDCNT3_A, DBPDCNT3_D6
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wait_timer WAIT_10KMCLK
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bra init_dbsc3_ctrl_533
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nop
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.align 2
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WAIT_200US_400: .long 40000
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WAIT_200US_533: .long 53300
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WAIT_100US_400: .long 20000
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WAIT_100US_533: .long 26650
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WAIT_32MCLK: .long 32
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WAIT_16MCLK: .long 16
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WAIT_1MCLK: .long 1
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WAIT_10KMCLK: .long 10000
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DBPDCNT0_A: .long 0xFE800200
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DBPDCNT0_D_533: .long 0x00010245
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DBPDCNT0_D_400: .long 0x00010235
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DBPDCNT1_A: .long 0xFE800204
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DBPDCNT1_D: .long 0x00000014
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DBPDCNT3_A: .long 0xFE80020C
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DBPDCNT3_D: .long 0x80000000
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DBPDCNT3_D0: .long 0x800F0000
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DBPDCNT3_D1: .long 0x800F1000
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DBPDCNT3_D2: .long 0x820F1000
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DBPDCNT3_D3: .long 0x860F1000
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DBPDCNT3_D4: .long 0x870F1000
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DBPDCNT3_D5: .long 0x870F3000
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DBPDCNT3_D6: .long 0x870F7000
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init_dbsc3_ctrl_400:
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write32 DBKIND_A, DBKIND_D
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write32 DBCONF_A, DBCONF_D
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write32 DBTR0_A, DBTR0_D_400
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write32 DBTR1_A, DBTR1_D_400
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write32 DBTR2_A, DBTR2_D
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write32 DBTR3_A, DBTR3_D_400
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write32 DBTR4_A, DBTR4_D_400
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write32 DBTR5_A, DBTR5_D_400
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write32 DBTR6_A, DBTR6_D_400
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write32 DBTR7_A, DBTR7_D
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write32 DBTR8_A, DBTR8_D_400
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write32 DBTR9_A, DBTR9_D
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write32 DBTR10_A, DBTR10_D_400
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write32 DBTR11_A, DBTR11_D
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write32 DBTR12_A, DBTR12_D_400
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write32 DBTR13_A, DBTR13_D_400
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write32 DBTR14_A, DBTR14_D
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write32 DBTR15_A, DBTR15_D
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write32 DBTR16_A, DBTR16_D_400
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write32 DBTR17_A, DBTR17_D_400
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write32 DBTR18_A, DBTR18_D_400
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write32 DBBL_A, DBBL_D
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write32 DBRNK0_A, DBRNK0_D
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write32 DBCMD_A, DBCMD_D0_400
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write32 DBCMD_A, DBCMD_D1
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write32 DBCMD_A, DBCMD_D2
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write32 DBCMD_A, DBCMD_D3
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write32 DBCMD_A, DBCMD_D4
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write32 DBCMD_A, DBCMD_D5_400
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write32 DBCMD_A, DBCMD_D6
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write32 DBCMD_A, DBCMD_D7
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write32 DBCMD_A, DBCMD_D8
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write32 DBCMD_A, DBCMD_D9_400
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write32 DBCMD_A, DBCMD_D10
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write32 DBCMD_A, DBCMD_D11
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write32 DBCMD_A, DBCMD_D12
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write32 DBRFCNF0_A, DBRFCNF0_D
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write32 DBRFCNF1_A, DBRFCNF1_D_400
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write32 DBRFCNF2_A, DBRFCNF2_D
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write32 DBRFEN_A, DBRFEN_D
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write32 DBACEN_A, DBACEN_D
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write32 DBACEN_A, DBACEN_D
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/* Dummy read */
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mov.l DBWAIT_A, r1
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synco
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mov.l @r1, r0
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synco
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/* Dummy read */
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mov.l SDRAM_A, r1
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synco
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mov.l @r1, r0
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synco
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/* need sleep 186A0 */
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bra finish_init_sh7734
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nop
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.align 2
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init_dbsc3_ctrl_533:
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write32 DBKIND_A, DBKIND_D
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write32 DBCONF_A, DBCONF_D
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write32 DBTR0_A, DBTR0_D_533
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write32 DBTR1_A, DBTR1_D_533
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write32 DBTR2_A, DBTR2_D
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write32 DBTR3_A, DBTR3_D_533
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write32 DBTR4_A, DBTR4_D_533
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write32 DBTR5_A, DBTR5_D_533
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write32 DBTR6_A, DBTR6_D_533
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write32 DBTR7_A, DBTR7_D
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write32 DBTR8_A, DBTR8_D_533
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write32 DBTR9_A, DBTR9_D
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write32 DBTR10_A, DBTR10_D_533
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write32 DBTR11_A, DBTR11_D
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write32 DBTR12_A, DBTR12_D_533
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write32 DBTR13_A, DBTR13_D_533
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write32 DBTR14_A, DBTR14_D
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write32 DBTR15_A, DBTR15_D
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write32 DBTR16_A, DBTR16_D_533
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write32 DBTR17_A, DBTR17_D_533
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write32 DBTR18_A, DBTR18_D_533
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write32 DBBL_A, DBBL_D
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write32 DBRNK0_A, DBRNK0_D
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write32 DBCMD_A, DBCMD_D0_533
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write32 DBCMD_A, DBCMD_D1
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write32 DBCMD_A, DBCMD_D2
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write32 DBCMD_A, DBCMD_D3
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write32 DBCMD_A, DBCMD_D4
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write32 DBCMD_A, DBCMD_D5_533
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write32 DBCMD_A, DBCMD_D6
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write32 DBCMD_A, DBCMD_D7
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write32 DBCMD_A, DBCMD_D8
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write32 DBCMD_A, DBCMD_D9_533
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write32 DBCMD_A, DBCMD_D10
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write32 DBCMD_A, DBCMD_D11
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write32 DBCMD_A, DBCMD_D12
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write32 DBRFCNF0_A, DBRFCNF0_D
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write32 DBRFCNF1_A, DBRFCNF1_D_533
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write32 DBRFCNF2_A, DBRFCNF2_D
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write32 DBRFEN_A, DBRFEN_D
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write32 DBACEN_A, DBACEN_D
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write32 DBACEN_A, DBACEN_D
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/* Dummy read */
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mov.l DBWAIT_A, r1
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synco
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mov.l @r1, r0
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synco
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/* Dummy read */
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mov.l SDRAM_A, r1
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synco
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mov.l @r1, r0
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synco
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/* need sleep 186A0 */
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bra finish_init_sh7734
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nop
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.align 2
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DBKIND_A: .long 0xFE800020
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DBKIND_D: .long 0x00000005
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DBCONF_A: .long 0xFE800024
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DBCONF_D: .long 0x0D020A01
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DBTR0_A: .long 0xFE800040
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DBTR0_D_533:.long 0x00000004
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DBTR0_D_400:.long 0x00000003
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DBTR1_A: .long 0xFE800044
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DBTR1_D_533:.long 0x00000003
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DBTR1_D_400:.long 0x00000002
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DBTR2_A: .long 0xFE800048
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DBTR2_D: .long 0x00000000
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DBTR3_A: .long 0xFE800050
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DBTR3_D_533:.long 0x00000004
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DBTR3_D_400:.long 0x00000003
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DBTR4_A: .long 0xFE800054
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DBTR4_D_533:.long 0x00050004
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DBTR4_D_400:.long 0x00050003
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DBTR5_A: .long 0xFE800058
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DBTR5_D_533:.long 0x0000000F
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DBTR5_D_400:.long 0x0000000B
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DBTR6_A: .long 0xFE80005C
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DBTR6_D_533:.long 0x0000000B
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DBTR6_D_400:.long 0x00000008
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DBTR7_A: .long 0xFE800060
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DBTR7_D: .long 0x00000002
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DBTR8_A: .long 0xFE800064
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DBTR8_D_533:.long 0x0000000D
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DBTR8_D_400:.long 0x0000000A
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DBTR9_A: .long 0xFE800068
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DBTR9_D: .long 0x00000002
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DBTR10_A: .long 0xFE80006C
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DBTR10_D_533:.long 0x00000004
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DBTR10_D_400:.long 0x00000003
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DBTR11_A: .long 0xFE800070
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DBTR11_D: .long 0x00000008
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DBTR12_A: .long 0xFE800074
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DBTR12_D_533:.long 0x00000009
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DBTR12_D_400:.long 0x00000008
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DBTR13_A: .long 0xFE800078
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DBTR13_D_533:.long 0x00000022
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DBTR13_D_400:.long 0x0000001A
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DBTR14_A: .long 0xFE80007C
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DBTR14_D: .long 0x00070002
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DBTR15_A: .long 0xFE800080
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DBTR15_D: .long 0x00000003
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DBTR16_A: .long 0xFE800084
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DBTR16_D_533:.long 0x120A1001
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DBTR16_D_400:.long 0x12091001
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DBTR17_A: .long 0xFE800088
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DBTR17_D_533:.long 0x00040000
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DBTR17_D_400:.long 0x00030000
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DBTR18_A: .long 0xFE80008C
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DBTR18_D_533:.long 0x02010200
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DBTR18_D_400:.long 0x02000207
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DBBL_A: .long 0xFE8000B0
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DBBL_D: .long 0x00000000
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DBRNK0_A: .long 0xFE800100
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DBRNK0_D: .long 0x00000001
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DBCMD_A: .long 0xFE800018
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DBCMD_D0_533: .long 0x1100006B
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DBCMD_D0_400: .long 0x11000050
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DBCMD_D1: .long 0x0B000000
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DBCMD_D2: .long 0x2A004000
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DBCMD_D3: .long 0x2B006000
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DBCMD_D4: .long 0x29002044
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DBCMD_D5_533: .long 0x28000743
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DBCMD_D5_400: .long 0x28000533
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DBCMD_D6: .long 0x0B000000
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DBCMD_D7: .long 0x0C000000
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DBCMD_D8: .long 0x0C000000
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DBCMD_D9_533: .long 0x28000643
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DBCMD_D9_400: .long 0x28000433
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DBCMD_D10: .long 0x000000C8
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DBCMD_D11: .long 0x290023C4
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DBCMD_D12: .long 0x29002004
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DBRFCNF0_A: .long 0xFE8000E0
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DBRFCNF0_D: .long 0x000001FF
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DBRFCNF1_A: .long 0xFE8000E4
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DBRFCNF1_D_533: .long 0x00000805
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DBRFCNF1_D_400: .long 0x00000618
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DBRFCNF2_A: .long 0xFE8000E8
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DBRFCNF2_D: .long 0x00000000
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DBRFEN_A: .long 0xFE800014
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DBRFEN_D: .long 0x00000001
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DBACEN_A: .long 0xFE800010
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DBACEN_D: .long 0x00000001
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DBWAIT_A: .long 0xFE80001C
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SDRAM_A: .long 0x0C000000
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finish_init_sh7734:
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write32 CCR_A, CCR_D
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stc sr, r0
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mov.l SR_MASK_D, r1
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and r1, r0
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ldc r0, sr
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rts
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nop
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.align 2
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CCR_A: .long 0xFF00001C
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CCR_D: .long 0x0000090B
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SR_MASK_D: .long 0xEFFFFF0F
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