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![Simon Glass](/assets/img/avatar_default.png)
At present the debug UART is set up in sdram.c which is not the best place since it has nothing in particular to do with SDRAM. Since we want to support initing this in SPL too, move it to a common file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: added 'broadwell' tag in the commit title] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
207 lines
4.8 KiB
C
207 lines
4.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2016 Google, Inc
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*
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* From coreboot src/soc/intel/broadwell/romstage/raminit.c
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*/
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#include <common.h>
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#include <dm.h>
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#include <pci.h>
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#include <syscon.h>
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#include <asm/cpu.h>
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#include <asm/io.h>
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#include <asm/lpc_common.h>
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#include <asm/mrccache.h>
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#include <asm/mrc_common.h>
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#include <asm/mtrr.h>
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#include <asm/pci.h>
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#include <asm/arch/iomap.h>
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#include <asm/arch/me.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/pei_data.h>
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#include <asm/arch/pm.h>
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ulong board_get_usable_ram_top(ulong total_size)
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{
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return mrc_common_board_get_usable_ram_top(total_size);
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}
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int dram_init_banksize(void)
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{
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mrc_common_dram_init_banksize();
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return 0;
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}
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static unsigned long get_top_of_ram(struct udevice *dev)
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{
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/*
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* Base of DPR is top of usable DRAM below 4GiB. The register has
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* 1 MiB alignment and reports the TOP of the range, the base
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* must be calculated from the size in MiB in bits 11:4.
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*/
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u32 dpr, tom;
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dm_pci_read_config32(dev, DPR, &dpr);
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tom = dpr & ~((1 << 20) - 1);
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debug("dpt %08x tom %08x\n", dpr, tom);
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/* Subtract DMA Protected Range size if enabled */
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if (dpr & DPR_EPM)
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tom -= (dpr & DPR_SIZE_MASK) << 16;
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return (unsigned long)tom;
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}
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/**
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* sdram_find() - Find available memory
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*
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* This is a bit complicated since on x86 there are system memory holes all
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* over the place. We create a list of available memory blocks
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*
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* @dev: Northbridge device
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*/
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static int sdram_find(struct udevice *dev)
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{
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struct memory_info *info = &gd->arch.meminfo;
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ulong top_of_ram;
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top_of_ram = get_top_of_ram(dev);
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mrc_add_memory_area(info, 0, top_of_ram);
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/* Add MTRRs for memory */
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mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
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return 0;
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}
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static int prepare_mrc_cache(struct pei_data *pei_data)
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{
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struct mrc_data_container *mrc_cache;
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struct mrc_region entry;
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int ret;
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ret = mrccache_get_region(NULL, &entry);
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if (ret)
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return ret;
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mrc_cache = mrccache_find_current(&entry);
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if (!mrc_cache)
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return -ENOENT;
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pei_data->saved_data = mrc_cache->data;
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pei_data->saved_data_size = mrc_cache->data_size;
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debug("%s: at %p, size %x checksum %04x\n", __func__,
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pei_data->saved_data, pei_data->saved_data_size,
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mrc_cache->checksum);
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return 0;
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}
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int dram_init(void)
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{
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struct pei_data _pei_data __aligned(8);
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struct pei_data *pei_data = &_pei_data;
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struct udevice *dev, *me_dev, *pch_dev;
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struct chipset_power_state ps;
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const void *spd_data;
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int ret, size;
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memset(pei_data, '\0', sizeof(struct pei_data));
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/* Print ME state before MRC */
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ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
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if (ret) {
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debug("Cannot get ME (err=%d)\n", ret);
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return ret;
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}
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intel_me_status(me_dev);
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/* Save ME HSIO version */
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ret = uclass_first_device_err(UCLASS_PCH, &pch_dev);
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if (ret) {
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debug("Cannot get PCH (err=%d)\n", ret);
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return ret;
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}
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power_state_get(pch_dev, &ps);
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intel_me_hsio_version(me_dev, &ps.hsio_version, &ps.hsio_checksum);
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broadwell_fill_pei_data(pei_data);
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mainboard_fill_pei_data(pei_data);
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ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
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if (ret) {
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debug("Cannot get Northbridge (err=%d)\n", ret);
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return ret;
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}
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size = 256;
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ret = mrc_locate_spd(dev, size, &spd_data);
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if (ret) {
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debug("Cannot locate SPD (err=%d)\n", ret);
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return ret;
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}
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memcpy(pei_data->spd_data[0][0], spd_data, size);
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memcpy(pei_data->spd_data[1][0], spd_data, size);
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ret = prepare_mrc_cache(pei_data);
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if (ret)
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debug("prepare_mrc_cache failed: %d\n", ret);
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debug("PEI version %#x\n", pei_data->pei_version);
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ret = mrc_common_init(dev, pei_data, true);
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if (ret) {
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debug("mrc_common_init() failed(err=%d)\n", ret);
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return ret;
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}
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debug("Memory init done\n");
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ret = sdram_find(dev);
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if (ret) {
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debug("sdram_find() failed (err=%d)\n", ret);
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return ret;
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}
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gd->ram_size = gd->arch.meminfo.total_32bit_memory;
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debug("RAM size %llx\n", (unsigned long long)gd->ram_size);
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debug("MRC output data length %#x at %p\n", pei_data->data_to_save_size,
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pei_data->data_to_save);
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/* S3 resume: don't save scrambler seed or MRC data */
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if (pei_data->boot_mode != SLEEP_STATE_S3) {
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/*
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* This will be copied to SDRAM in reserve_arch(), then written
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* to SPI flash in mrccache_save()
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*/
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gd->arch.mrc_output = (char *)pei_data->data_to_save;
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gd->arch.mrc_output_len = pei_data->data_to_save_size;
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}
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gd->arch.pei_meminfo = pei_data->meminfo;
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return 0;
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}
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/* Use this hook to save our SDRAM parameters */
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int misc_init_r(void)
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{
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int ret;
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ret = mrccache_save();
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if (ret)
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printf("Unable to save MRC data: %d\n", ret);
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else
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debug("Saved MRC cache data\n");
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return 0;
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}
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static const struct udevice_id broadwell_syscon_ids[] = {
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{ .compatible = "intel,me", .data = X86_SYSCON_ME },
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{ }
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};
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U_BOOT_DRIVER(syscon_intel_me) = {
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.name = "intel_me_syscon",
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.id = UCLASS_SYSCON,
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.of_match = broadwell_syscon_ids,
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};
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