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https://github.com/brain-hackers/u-boot-brain
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51ea5a060d
The DRAM PHY layer on PH1-LD20 is able to calibrate PHY parameters periodically. This compensates for the voltage and temperature deviation and improves the PHY parameter adjustment. Instead, it requires 64 byte scratch memory in each DRAM channel for the dynamic training. The memory regions must be reserved in DT before jumping to the kernel. The scratch area can be anywhere in each DRAM channel, but the DRAM init code in SPL currently assigns it at the end of each channel. So, it makes sense to reserve the regions on run-time by U-Boot instead of statically embedding it in the DT in Linux. Anyway, a boot-loader should know much more about memory initialization than the kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
124 lines
2.5 KiB
C
124 lines
2.5 KiB
C
/*
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* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <fdtdec.h>
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#include <linux/err.h>
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#include "init.h"
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#include "soc-info.h"
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DECLARE_GLOBAL_DATA_PTR;
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static const void *get_memory_reg_prop(const void *fdt, int *lenp)
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{
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int offset;
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offset = fdt_path_offset(fdt, "/memory");
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if (offset < 0)
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return NULL;
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return fdt_getprop(fdt, offset, "reg", lenp);
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}
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int dram_init(void)
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{
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const void *fdt = gd->fdt_blob;
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const fdt32_t *val;
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int ac, sc, len;
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ac = fdt_address_cells(fdt, 0);
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sc = fdt_size_cells(fdt, 0);
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if (ac < 0 || sc < 1 || sc > 2) {
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printf("invalid address/size cells\n");
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return -EINVAL;
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}
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val = get_memory_reg_prop(fdt, &len);
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if (len / sizeof(*val) < ac + sc)
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return -EINVAL;
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val += ac;
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gd->ram_size = fdtdec_get_number(val, sc);
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debug("DRAM size = %08lx\n", (unsigned long)gd->ram_size);
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return 0;
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}
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void dram_init_banksize(void)
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{
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const void *fdt = gd->fdt_blob;
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const fdt32_t *val;
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int ac, sc, cells, len, i;
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val = get_memory_reg_prop(fdt, &len);
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if (len < 0)
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return;
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ac = fdt_address_cells(fdt, 0);
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sc = fdt_size_cells(fdt, 0);
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if (ac < 1 || sc > 2 || sc < 1 || sc > 2) {
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printf("invalid address/size cells\n");
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return;
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}
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cells = ac + sc;
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len /= sizeof(*val);
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for (i = 0; i < CONFIG_NR_DRAM_BANKS && len >= cells;
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i++, len -= cells) {
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gd->bd->bi_dram[i].start = fdtdec_get_number(val, ac);
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val += ac;
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gd->bd->bi_dram[i].size = fdtdec_get_number(val, sc);
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val += sc;
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debug("DRAM bank %d: start = %08lx, size = %08lx\n",
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i, (unsigned long)gd->bd->bi_dram[i].start,
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(unsigned long)gd->bd->bi_dram[i].size);
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}
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}
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#ifdef CONFIG_OF_BOARD_SETUP
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/*
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* The DRAM PHY requires 64 byte scratch area in each DRAM channel
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* for its dynamic PHY training feature.
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*/
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int ft_board_setup(void *fdt, bd_t *bd)
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{
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const struct uniphier_board_data *param;
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unsigned long rsv_addr;
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const unsigned long rsv_size = 64;
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int ch, ret;
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if (uniphier_get_soc_type() != SOC_UNIPHIER_LD20)
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return 0;
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param = uniphier_get_board_param();
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if (!param) {
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printf("failed to get board parameter\n");
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return -ENODEV;
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}
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for (ch = 0; ch < param->dram_nr_ch; ch++) {
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rsv_addr = param->dram_ch[ch].base + param->dram_ch[ch].size;
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rsv_addr -= rsv_size;
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ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size);
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if (ret)
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return -ENOSPC;
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printf(" Reserved memory region for DRAM PHY training: addr=%lx size=%lx\n",
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rsv_addr, rsv_size);
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}
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return 0;
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}
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#endif
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