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https://github.com/brain-hackers/u-boot-brain
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ab1b955211
For files like the drivers/serial/serial.c, it must include the platform file, as the CONFIG_SYS_NS16550_COM1 must reference to the definition in the platform definition files. Include the platform definition file in the config file, so that it would decouple the dependence for the driver files. Updated cpu.h to remove build errors for gplugd board (by prafulla) Signed-off-by: Lei Wen <leiwen@marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
109 lines
3.0 KiB
C
109 lines
3.0 KiB
C
/*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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* Contributor: Mahavir Jain <mjain@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/armada100.h>
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#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
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#define SET_MRVL_ID (1<<8)
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#define L2C_RAM_SEL (1<<4)
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int arch_cpu_init(void)
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{
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u32 val;
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struct armd1cpu_registers *cpuregs =
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(struct armd1cpu_registers *) ARMD1_CPU_BASE;
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struct armd1apb1_registers *apb1clkres =
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(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
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struct armd1mpmu_registers *mpmu =
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(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
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/* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
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val = readl(&cpuregs->cpu_conf);
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val = val | SET_MRVL_ID;
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writel(val, &cpuregs->cpu_conf);
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/* Enable Clocks for all hardware units */
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writel(0xFFFFFFFF, &mpmu->acgr);
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/* Turn on AIB and AIB-APB Functional clock */
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writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
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/* ensure L2 cache is not mapped as SRAM */
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val = readl(&cpuregs->cpu_conf);
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val = val & ~(L2C_RAM_SEL);
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writel(val, &cpuregs->cpu_conf);
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/* Enable GPIO clock */
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writel(APBC_APBCLK, &apb1clkres->gpio);
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#ifdef CONFIG_I2C_MV
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/* Enable general I2C clock */
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writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
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writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
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/* Enable power I2C clock */
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writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
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writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
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#endif
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/*
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* Enable Functional and APB clock at 14.7456MHz
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* for configured UART console
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*/
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#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
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writel(UARTCLK14745KHZ, &apb1clkres->uart3);
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#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
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writel(UARTCLK14745KHZ, &apb1clkres->uart2);
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#else
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writel(UARTCLK14745KHZ, &apb1clkres->uart1);
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#endif
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icache_enable();
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return 0;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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u32 id;
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struct armd1cpu_registers *cpuregs =
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(struct armd1cpu_registers *) ARMD1_CPU_BASE;
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id = readl(&cpuregs->chip_id);
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printf("SoC: Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
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return 0;
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}
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#endif
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#ifdef CONFIG_I2C_MV
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void i2c_clk_enable(void)
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{
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}
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#endif
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