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https://github.com/brain-hackers/u-boot-brain
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486544161f
Port hypervisor related code from Mini-OS. This is referencing the code of Mini-OS from [1] by Huang Shijie and Volodymyr Babchuk which is for ARM64. Update essential arch code to support required bit operations, memory barriers etc. Copyright for the bits ported belong to at least the following authors, please see related files for details: Copyright (c) 2002-2003, K A Fraser Copyright (c) 2005, Grzegorz Milos, gm281@cam.ac.uk,Intel Research Cambridge Copyright (c) 2014, Karim Allah Ahmed <karim.allah.ahmed@gmail.com> [1] - https://github.com/zyzii/mini-os.git Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com> Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com> [trini: Drop wmb() from musb-net/linux-compat.h now] Signed-off-by: Tom Rini <trini@konsulko.com>
89 lines
2.4 KiB
C
89 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* (C) 2014 Karim Allah Ahmed <karim.allah.ahmed@gmail.com>
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* (C) 2020, EPAM Systems Inc.
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*/
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#ifndef _ASM_ARM_XEN_SYSTEM_H
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#define _ASM_ARM_XEN_SYSTEM_H
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#include <compiler.h>
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#include <asm/bitops.h>
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/* If *ptr == old, then store new there (and return new).
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* Otherwise, return the old value.
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* Atomic.
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*/
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#define synch_cmpxchg(ptr, old, new) \
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({ __typeof__(*ptr) stored = old; \
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__atomic_compare_exchange_n(ptr, &stored, new, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST) ? new : old; \
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})
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/* As test_and_clear_bit, but using __ATOMIC_SEQ_CST */
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static inline int synch_test_and_clear_bit(int nr, volatile void *addr)
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{
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u8 *byte = ((u8 *)addr) + (nr >> 3);
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u8 bit = 1 << (nr & 7);
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u8 orig;
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orig = __atomic_fetch_and(byte, ~bit, __ATOMIC_SEQ_CST);
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return (orig & bit) != 0;
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}
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/* As test_and_set_bit, but using __ATOMIC_SEQ_CST */
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static inline int synch_test_and_set_bit(int nr, volatile void *base)
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{
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u8 *byte = ((u8 *)base) + (nr >> 3);
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u8 bit = 1 << (nr & 7);
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u8 orig;
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orig = __atomic_fetch_or(byte, bit, __ATOMIC_SEQ_CST);
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return (orig & bit) != 0;
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}
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/* As set_bit, but using __ATOMIC_SEQ_CST */
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static inline void synch_set_bit(int nr, volatile void *addr)
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{
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synch_test_and_set_bit(nr, addr);
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}
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/* As clear_bit, but using __ATOMIC_SEQ_CST */
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static inline void synch_clear_bit(int nr, volatile void *addr)
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{
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synch_test_and_clear_bit(nr, addr);
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}
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/* As test_bit, but with a following memory barrier. */
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//static inline int synch_test_bit(int nr, volatile void *addr)
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static inline int synch_test_bit(int nr, const void *addr)
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{
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int result;
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result = test_bit(nr, addr);
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barrier();
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return result;
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}
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#define xchg(ptr, v) __atomic_exchange_n(ptr, v, __ATOMIC_SEQ_CST)
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#define xchg(ptr, v) __atomic_exchange_n(ptr, v, __ATOMIC_SEQ_CST)
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#define xen_mb() mb()
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#define xen_rmb() rmb()
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#define xen_wmb() wmb()
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#define to_phys(x) ((unsigned long)(x))
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#define to_virt(x) ((void *)(x))
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#define PFN_UP(x) (unsigned long)(((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
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#define PFN_DOWN(x) (unsigned long)((x) >> PAGE_SHIFT)
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#define PFN_PHYS(x) ((unsigned long)(x) << PAGE_SHIFT)
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#define PHYS_PFN(x) (unsigned long)((x) >> PAGE_SHIFT)
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#define virt_to_pfn(_virt) (PFN_DOWN(to_phys(_virt)))
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#define virt_to_mfn(_virt) (PFN_DOWN(to_phys(_virt)))
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#define mfn_to_virt(_mfn) (to_virt(PFN_PHYS(_mfn)))
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#define pfn_to_virt(_pfn) (to_virt(PFN_PHYS(_pfn)))
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#endif
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