mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-01 07:43:45 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
66 lines
1.7 KiB
C
66 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Auther:
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* Vaibhav Hiremath <hvaibhav@ti.com>
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*
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* Copyright (C) 2010
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* Texas Instruments Incorporated - http://www.ti.com/
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*/
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#ifndef _EMIF_H_
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#define _EMIF_H_
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/*
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* Configuration values
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*/
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#define EMIF4_TIM1_T_RP (0x3 << 25)
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#define EMIF4_TIM1_T_RCD (0x3 << 21)
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#define EMIF4_TIM1_T_WR (0x3 << 17)
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#define EMIF4_TIM1_T_RAS (0x8 << 12)
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#define EMIF4_TIM1_T_RC (0xA << 6)
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#define EMIF4_TIM1_T_RRD (0x2 << 3)
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#define EMIF4_TIM1_T_WTR (0x2)
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#define EMIF4_TIM2_T_XP (0x2 << 28)
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#define EMIF4_TIM2_T_ODT (0x0 << 25)
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#define EMIF4_TIM2_T_XSNR (0x1C << 16)
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#define EMIF4_TIM2_T_XSRD (0xC8 << 6)
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#define EMIF4_TIM2_T_RTP (0x1 << 3)
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#define EMIF4_TIM2_T_CKE (0x2)
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#define EMIF4_TIM3_T_RFC (0x25 << 4)
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#define EMIF4_TIM3_T_RAS_MAX (0x7)
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#define EMIF4_PWR_IDLE_MODE (0x2 << 30)
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#define EMIF4_PWR_DPD_DIS (0x0 << 10)
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#define EMIF4_PWR_DPD_EN (0x1 << 10)
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#define EMIF4_PWR_LP_MODE (0x0 << 8)
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#define EMIF4_PWR_PM_TIM (0x0)
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#define EMIF4_INITREF_DIS (0x0 << 31)
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#define EMIF4_REFRESH_RATE (0x50F)
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#define EMIF4_CFG_SDRAM_TYP (0x2 << 29)
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#define EMIF4_CFG_IBANK_POS (0x0 << 27)
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#define EMIF4_CFG_DDR_TERM (0x0 << 24)
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#define EMIF4_CFG_DDR2_DDQS (0x1 << 23)
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#define EMIF4_CFG_DDR_DIS_DLL (0x0 << 20)
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#define EMIF4_CFG_SDR_DRV (0x0 << 18)
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#define EMIF4_CFG_NARROW_MD (0x0 << 14)
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#define EMIF4_CFG_CL (0x5 << 10)
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#define EMIF4_CFG_ROWSIZE (0x0 << 7)
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#define EMIF4_CFG_IBANK (0x3 << 4)
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#define EMIF4_CFG_EBANK (0x0 << 3)
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#define EMIF4_CFG_PGSIZE (0x2)
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/*
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* EMIF4 PHY Control 1 register configuration
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*/
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#define EMIF4_DDR1_EXT_STRB_EN (0x1 << 7)
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#define EMIF4_DDR1_EXT_STRB_DIS (0x0 << 7)
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#define EMIF4_DDR1_PWRDN_DIS (0x0 << 6)
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#define EMIF4_DDR1_PWRDN_EN (0x1 << 6)
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#define EMIF4_DDR1_READ_LAT (0x6 << 0)
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#endif /* endif _EMIF_H_ */
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