mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
348 lines
7.9 KiB
C
348 lines
7.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*/
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#ifndef _CLOCKS_OMAP3_H_
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#define _CLOCKS_OMAP3_H_
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#define PLL_STOP 1 /* PER & IVA */
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#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */
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#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */
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#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */
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/*
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* The following configurations are OPP and SysClk value independant
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* and hence are defined here. All the other DPLL related values are
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* tabulated in lowlevel_init.S.
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*/
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/* CORE DPLL */
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#define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */
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#define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */
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#define CORE_FUSB_DIV 2 /* 41.5MHz: */
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#define CORE_L4_DIV 2 /* 83MHz : L4 */
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#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */
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#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */
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#define GFX_DIV_36X 5 /* 200MHz : CM_CLKSEL_GFX */
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#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */
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/* PER DPLL */
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#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */
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#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */
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#define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */
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#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */
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#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50))
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/* MPU DPLL */
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#define MPU_M_12_ES1 0x0FE
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#define MPU_N_12_ES1 0x07
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#define MPU_FSEL_12_ES1 0x05
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#define MPU_M2_12_ES1 0x01
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#define MPU_M_12_ES2 0x0FA
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#define MPU_N_12_ES2 0x05
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#define MPU_FSEL_12_ES2 0x07
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#define MPU_M2_ES2 0x01
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#define MPU_M_12 0x085
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#define MPU_N_12 0x05
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#define MPU_FSEL_12 0x07
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#define MPU_M2_12 0x01
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#define MPU_M_13_ES1 0x17D
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#define MPU_N_13_ES1 0x0C
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#define MPU_FSEL_13_ES1 0x03
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#define MPU_M2_13_ES1 0x01
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#define MPU_M_13_ES2 0x258
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#define MPU_N_13_ES2 0x0C
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#define MPU_FSEL_13_ES2 0x03
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#define MPU_M2_13_ES2 0x01
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#define MPU_M_13 0x10A
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#define MPU_N_13 0x0C
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#define MPU_FSEL_13 0x03
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#define MPU_M2_13 0x01
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#define MPU_M_19P2_ES1 0x179
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#define MPU_N_19P2_ES1 0x12
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#define MPU_FSEL_19P2_ES1 0x04
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#define MPU_M2_19P2_ES1 0x01
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#define MPU_M_19P2_ES2 0x271
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#define MPU_N_19P2_ES2 0x17
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#define MPU_FSEL_19P2_ES2 0x03
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#define MPU_M2_19P2_ES2 0x01
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#define MPU_M_19P2 0x14C
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#define MPU_N_19P2 0x17
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#define MPU_FSEL_19P2 0x03
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#define MPU_M2_19P2 0x01
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#define MPU_M_26_ES1 0x17D
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#define MPU_N_26_ES1 0x19
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#define MPU_FSEL_26_ES1 0x03
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#define MPU_M2_26_ES1 0x01
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#define MPU_M_26_ES2 0x0FA
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#define MPU_N_26_ES2 0x0C
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#define MPU_FSEL_26_ES2 0x07
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#define MPU_M2_26_ES2 0x01
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#define MPU_M_26 0x085
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#define MPU_N_26 0x0C
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#define MPU_FSEL_26 0x07
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#define MPU_M2_26 0x01
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#define MPU_M_38P4_ES1 0x1FA
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#define MPU_N_38P4_ES1 0x32
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#define MPU_FSEL_38P4_ES1 0x03
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#define MPU_M2_38P4_ES1 0x01
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#define MPU_M_38P4_ES2 0x271
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#define MPU_N_38P4_ES2 0x2F
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#define MPU_FSEL_38P4_ES2 0x03
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#define MPU_M2_38P4_ES2 0x01
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#define MPU_M_38P4 0x14C
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#define MPU_N_38P4 0x2F
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#define MPU_FSEL_38P4 0x03
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#define MPU_M2_38P4 0x01
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/* IVA DPLL */
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#define IVA_M_12_ES1 0x07D
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#define IVA_N_12_ES1 0x05
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#define IVA_FSEL_12_ES1 0x07
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#define IVA_M2_12_ES1 0x01
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#define IVA_M_12_ES2 0x0B4
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#define IVA_N_12_ES2 0x05
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#define IVA_FSEL_12_ES2 0x07
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#define IVA_M2_12_ES2 0x01
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#define IVA_M_12 0x085
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#define IVA_N_12 0x05
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#define IVA_FSEL_12 0x07
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#define IVA_M2_12 0x01
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#define IVA_M_13_ES1 0x0FA
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#define IVA_N_13_ES1 0x0C
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#define IVA_FSEL_13_ES1 0x03
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#define IVA_M2_13_ES1 0x01
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#define IVA_M_13_ES2 0x168
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#define IVA_N_13_ES2 0x0C
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#define IVA_FSEL_13_ES2 0x03
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#define IVA_M2_13_ES2 0x01
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#define IVA_M_13 0x10A
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#define IVA_N_13 0x0C
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#define IVA_FSEL_13 0x03
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#define IVA_M2_13 0x01
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#define IVA_M_19P2_ES1 0x082
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#define IVA_N_19P2_ES1 0x09
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#define IVA_FSEL_19P2_ES1 0x07
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#define IVA_M2_19P2_ES1 0x01
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#define IVA_M_19P2_ES2 0x0E1
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#define IVA_N_19P2_ES2 0x0B
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#define IVA_FSEL_19P2_ES2 0x06
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#define IVA_M2_19P2_ES2 0x01
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#define IVA_M_19P2 0x14C
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#define IVA_N_19P2 0x17
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#define IVA_FSEL_19P2 0x03
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#define IVA_M2_19P2 0x01
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#define IVA_M_26_ES1 0x07D
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#define IVA_N_26_ES1 0x0C
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#define IVA_FSEL_26_ES1 0x07
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#define IVA_M2_26_ES1 0x01
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#define IVA_M_26_ES2 0x0B4
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#define IVA_N_26_ES2 0x0C
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#define IVA_FSEL_26_ES2 0x07
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#define IVA_M2_26_ES2 0x01
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#define IVA_M_26 0x085
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#define IVA_N_26 0x0C
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#define IVA_FSEL_26 0x07
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#define IVA_M2_26 0x01
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#define IVA_M_38P4_ES1 0x13F
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#define IVA_N_38P4_ES1 0x30
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#define IVA_FSEL_38P4_ES1 0x03
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#define IVA_M2_38P4_ES1 0x01
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#define IVA_M_38P4_ES2 0x0E1
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#define IVA_N_38P4_ES2 0x17
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#define IVA_FSEL_38P4_ES2 0x06
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#define IVA_M2_38P4_ES2 0x01
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#define IVA_M_38P4 0x14C
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#define IVA_N_38P4 0x2F
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#define IVA_FSEL_38P4 0x03
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#define IVA_M2_38P4 0x01
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/* CORE DPLL */
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#define CORE_M_12 0xA6
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#define CORE_N_12 0x05
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#define CORE_FSEL_12 0x07
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#define CORE_M2_12 0x01 /* M3 of 2 */
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#define CORE_M_12_ES1 0x19F
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#define CORE_N_12_ES1 0x0E
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#define CORE_FSL_12_ES1 0x03
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#define CORE_M2_12_ES1 0x1 /* M3 of 2 */
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#define CORE_M_13 0x14C
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#define CORE_N_13 0x0C
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#define CORE_FSEL_13 0x03
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#define CORE_M2_13 0x01 /* M3 of 2 */
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#define CORE_M_13_ES1 0x1B2
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#define CORE_N_13_ES1 0x10
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#define CORE_FSL_13_ES1 0x03
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#define CORE_M2_13_ES1 0x01 /* M3 of 2 */
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#define CORE_M_19P2 0x19F
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#define CORE_N_19P2 0x17
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#define CORE_FSEL_19P2 0x03
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#define CORE_M2_19P2 0x01 /* M3 of 2 */
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#define CORE_M_19P2_ES1 0x19F
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#define CORE_N_19P2_ES1 0x17
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#define CORE_FSL_19P2_ES1 0x03
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#define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */
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#define CORE_M_26 0xA6
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#define CORE_N_26 0x0C
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#define CORE_FSEL_26 0x07
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#define CORE_M2_26 0x01 /* M3 of 2 */
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#define CORE_M_26_ES1 0x1B2
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#define CORE_N_26_ES1 0x21
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#define CORE_FSL_26_ES1 0x03
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#define CORE_M2_26_ES1 0x01 /* M3 of 2 */
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#define CORE_M_38P4 0x19F
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#define CORE_N_38P4 0x2F
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#define CORE_FSEL_38P4 0x03
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#define CORE_M2_38P4 0x01 /* M3 of 2 */
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#define CORE_M_38P4_ES1 0x19F
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#define CORE_N_38P4_ES1 0x2F
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#define CORE_FSL_38P4_ES1 0x03
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#define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */
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/* PER DPLL */
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#define PER_M_12 0xD8
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#define PER_N_12 0x05
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#define PER_FSEL_12 0x07
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#define PER_M2_12 0x09
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#define PER_M_13 0x1B0
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#define PER_N_13 0x0C
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#define PER_FSEL_13 0x03
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#define PER_M2_13 0x09
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#define PER_M_19P2 0xE1
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#define PER_N_19P2 0x09
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#define PER_FSEL_19P2 0x07
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#define PER_M2_19P2 0x09
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#define PER_M_26 0xD8
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#define PER_N_26 0x0C
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#define PER_FSEL_26 0x07
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#define PER_M2_26 0x09
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#define PER_M_38P4 0xE1
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#define PER_N_38P4 0x13
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#define PER_FSEL_38P4 0x07
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#define PER_M2_38P4 0x09
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/* PER2 DPLL */
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#define PER2_M_12 0x78
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#define PER2_N_12 0x0B
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#define PER2_FSEL_12 0x03
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#define PER2_M2_12 0x01
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#define PER2_M_13 0x78
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#define PER2_N_13 0x0C
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#define PER2_FSEL_13 0x03
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#define PER2_M2_13 0x01
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#define PER2_M_19P2 0x2EE
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#define PER2_N_19P2 0x0B
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#define PER2_FSEL_19P2 0x06
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#define PER2_M2_19P2 0x0A
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#define PER2_M_26 0x78
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#define PER2_N_26 0x0C
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#define PER2_FSEL_26 0x03
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#define PER2_M2_26 0x01
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#define PER2_M_38P4 0x2EE
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#define PER2_N_38P4 0x0B
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#define PER2_FSEL_38P4 0x06
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#define PER2_M2_38P4 0x0A
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/* 36XX PER DPLL */
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#define PER_36XX_M_12 0x1B0
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#define PER_36XX_N_12 0x05
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#define PER_36XX_FSEL_12 0x07
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#define PER_36XX_M2_12 0x09
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#define PER_36XX_M_13 0x360
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#define PER_36XX_N_13 0x0C
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#define PER_36XX_FSEL_13 0x03
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#define PER_36XX_M2_13 0x09
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#define PER_36XX_M_19P2 0x1C2
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#define PER_36XX_N_19P2 0x09
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#define PER_36XX_FSEL_19P2 0x07
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#define PER_36XX_M2_19P2 0x09
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#define PER_36XX_M_26 0x1B0
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#define PER_36XX_N_26 0x0C
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#define PER_36XX_FSEL_26 0x07
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#define PER_36XX_M2_26 0x09
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#define PER_36XX_M_38P4 0x1C2
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#define PER_36XX_N_38P4 0x13
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#define PER_36XX_FSEL_38P4 0x07
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#define PER_36XX_M2_38P4 0x09
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/* 36XX PER2 DPLL */
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#define PER2_36XX_M_12 0x50
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#define PER2_36XX_N_12 0x00
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#define PER2_36XX_M2_12 0x08
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#define PER2_36XX_M_13 0x1BB
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#define PER2_36XX_N_13 0x05
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#define PER2_36XX_M2_13 0x08
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#define PER2_36XX_M_19P2 0x32
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#define PER2_36XX_N_19P2 0x00
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#define PER2_36XX_M2_19P2 0x08
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#define PER2_36XX_M_26 0x1BB
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#define PER2_36XX_N_26 0x0B
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#define PER2_36XX_M2_26 0x08
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#define PER2_36XX_M_38P4 0x19
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#define PER2_36XX_N_38P4 0x00
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#define PER2_36XX_M2_38P4 0x08
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#endif /* endif _CLOCKS_OMAP3_H_ */
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