mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
60 lines
1.7 KiB
C
60 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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* Contributor: Mahavir Jain <mjain@marvell.com>
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*/
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#ifndef _ASM_ARCH_ARMADA100_H
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#define _ASM_ARCH_ARMADA100_H
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#if defined (CONFIG_ARMADA100)
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/* Common APB clock register bit definitions */
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#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
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#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
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#define APBC_RST (1<<2) /* Reset Generation */
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/* Functional Clock Selection Mask */
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#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
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/* Fast Ethernet Controller Clock register definition */
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#define FE_CLK_RST 0x1
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#define FE_CLK_ENA 0x8
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/* SSP2 Clock Control */
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#define SSP2_APBCLK 0x01
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#define SSP2_FNCLK 0x02
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/* USB Clock/reset control bits */
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#define USB_SPH_AXICLK_EN 0x10
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#define USB_SPH_AXI_RST 0x02
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/* MPMU Clocks */
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#define APB2_26M_EN (1 << 20)
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#define AP_26M (1 << 4)
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/* Register Base Addresses */
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#define ARMD1_DRAM_BASE 0xB0000000
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#define ARMD1_FEC_BASE 0xC0800000
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#define ARMD1_TIMER_BASE 0xD4014000
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#define ARMD1_APBC1_BASE 0xD4015000
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#define ARMD1_APBC2_BASE 0xD4015800
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#define ARMD1_UART1_BASE 0xD4017000
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#define ARMD1_UART2_BASE 0xD4018000
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#define ARMD1_GPIO_BASE 0xD4019000
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#define ARMD1_SSP1_BASE 0xD401B000
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#define ARMD1_SSP2_BASE 0xD401C000
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#define ARMD1_MFPR_BASE 0xD401E000
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#define ARMD1_SSP3_BASE 0xD401F000
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#define ARMD1_SSP4_BASE 0xD4020000
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#define ARMD1_SSP5_BASE 0xD4021000
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#define ARMD1_UART3_BASE 0xD4026000
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#define ARMD1_MPMU_BASE 0xD4050000
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#define ARMD1_USB_HOST_BASE 0xD4209000
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#define ARMD1_APMU_BASE 0xD4282800
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#define ARMD1_CPU_BASE 0xD4282C00
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#endif /* CONFIG_ARMADA100 */
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#endif /* _ASM_ARCH_ARMADA100_H */
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