mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-20 18:17:59 +09:00
5318f18d2c
Every pin can be configured now from the device tree. A dt-bindings has been added to describe the different property available. Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975 Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Simon Glass <sjg@chromium.org>
132 lines
2.0 KiB
Plaintext
132 lines
2.0 KiB
Plaintext
/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/x86-gpio.h>
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/include/ "skeleton.dtsi"
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/include/ "serial.dtsi"
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/ {
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model = "Intel Minnowboard Max";
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compatible = "intel,minnowmax", "intel,baytrail";
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aliases {
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serial0 = &serial;
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spi0 = "/spi";
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};
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config {
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silent_console = <0>;
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};
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pch_pinctrl {
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compatible = "intel,x86-pinctrl";
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io-base = <0x4c>;
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pin_usb_host_en0@0 {
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gpio-offset = <0x80 8>;
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pad-offset = <0x260>;
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mode-gpio;
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output-value = <1>;
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direction = <PIN_OUTPUT>;
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};
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pin_usb_host_en1@0 {
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gpio-offset = <0x80 9>;
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pad-offset = <0x258>;
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mode-gpio;
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output-value = <1>;
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direction = <PIN_OUTPUT>;
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};
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};
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gpioa {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0 0x20>;
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bank-name = "A";
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};
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gpiob {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x20 0x20>;
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bank-name = "B";
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};
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gpioc {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x40 0x20>;
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bank-name = "C";
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};
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gpiod {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x60 0x20>;
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bank-name = "D";
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};
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gpioe {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x80 0x20>;
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bank-name = "E";
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};
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gpiof {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0xA0 0x20>;
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bank-name = "F";
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};
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chosen {
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stdout-path = "/serial";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "intel,baytrail-cpu";
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reg = <0>;
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intel,apic-id = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "intel,baytrail-cpu";
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reg = <1>;
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intel,apic-id = <4>;
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};
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};
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ich-spi";
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spi-flash@0 {
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reg = <0>;
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compatible = "stmicro,n25q064a", "spi-flash";
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memory-map = <0xff800000 0x00800000>;
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};
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};
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microcode {
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update@0 {
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#include "microcode/m0130673322.dtsi"
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};
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};
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};
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